peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 164

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

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Table 45
Register
FMR0
FMR1
FMR2
SIC1
SIC2,
SIC3
LOOP
FMR4
FMR5
XC0
XC1
RC0
RC1
IDLE
ICB 1
CCB 1
LIM0
LIM1
PCD
PCR
XPM2...0
IMR0-4
RTR1-4
TTR1-4
MODE
RAH1/2
RAL1/2
Data Sheet
3
3
Initial Values after reset and FMR1.PMOD = 1 (T1/J1)
Initiated
Value
00
10
00
00
00
00
00
00
00
00
9C
00
9C
00
00
00
00
00
00
00
7B
FF
00
00
FD
FF
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
,03
,FF
,FF
H
H
H
,00
H
Meaning
NRZ coding, no alarm simulation; XL1/2 stay tristate
PCM 24 mode, 4.096 Mbit/s system data rate, no AIS
transmission to remote end or system interface, payload
loop off, channel translation mode 0
8.192-MHz system clocking rate, Receive Buffer 2
Frames, Transmit Buffer bypass, Automatic freeze
signaling, data is active in the first channel phase
Channel loop back is disabled.
Remote alarm indication towards remote end disabled.
LFA condition: 2 out of 4 framing bits, Non-auto-
synchronization mode, F12 multiframing, internal bit-
robbing access disabled
The transmit clock slot offset is cleared.
The transmit time slot offset is cleared.
The receive clock slot offset is cleared.
The receive time slot offset is cleared.
Idle channel code is cleared.
Normal operation (no “Idle Channels” selected).
Normal operation (no clear channel operation).
Slave Mode, Local Loop off, CLKX=2.048 MHz active
high,
short haul mode, no LOS indication on RCLK
Analog interface selected, Remote Loop off
Pulse Count for LOS Detection cleared
Pulse Count for LOS Recovery cleared
Transmit Pulse Mask
All interrupts are disabled
No time slots selected
Signaling controller disabled
Compare register for receive address cleared
164
Operational Description T1/J1
FALC-LH V1.3
PEB 2255
2000-07