peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 160

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

set up, for example, may be programmed simultaneously. The bit FMR1.PMOD should
always be kept low (otherwise T1/J1 mode is selected).
Table 40
Basic Set Up
Mode Select
Specification of Line interface and clock
generation
Line interface coding
Loss of Signal detection/recovery
conditions
System interface mode
Transmit offset counters
Receive offset counters
AIS to system interface
Operational Set Up
Select framing
Framing additions
Synchronization mode
Signaling mode
Features like channel loop back, idle channel activation, extensions for signaling
support, alarm simulation, … may be activated later. Transmission of alarms (e.g. AIS,
remote alarm) and control of synchronization in connection with consequent actions to
remote end and internal system depend on the activation procedure selected.
Note: Read access to unused register addresses: value should be ignored.
Specific E1 Register Settings
The following is a suggestion for a basic initialization to meet most of the E1
requirements. Depending on different applications and requirement any other
initialization can be used.
Data Sheet
Write access to unused register addresses: should be avoided, or set to ‘00’ hex.
All control registers (except XFIFO, XS1-16, CMDR, DEC) are of type: Read/
Write.
Initialization Parameters (E1)
160
E1
FMR1.PMOD = 0
LIM0, LIM1, XPM2...0
FMR0.XC1/0, FMR0.RC1/0
PCD, PCR, LIM1, LIM2
FMR1.IMOD
XC0.XCO, XC1.XTO
RC0.RCO, RC1.RTO
FMR2.DAIS/SAIS
E1
FMR2.RFS1/0, FMR1.XFS
RC1.ASY4, RC1.SWD
FMR1.AFR, FMR2.ALMF
XSP, XSW, FMR1.ENSA, XSA8...4,
TSWM, MODE, CCR1, CCR3, PRE,
RAH1/2, RAL1/2
Operational Description E1
FALC-LH V1.3
PEB 2255
2000-07