peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 204

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

XCOS…
XTO5...0…
Receive Control 0 (Read/Write)
Value after RESET: 00
RCOS…
SICS…
Data Sheet
initialized or when the buffer should be centered. As a consequence a transmit slip
occurs.
RC0
RCOS
7
Transmit Clock Offset Shift
Only valid if SIC1.SXSC = 0.
0…
1…
Transmit Time Slot Offset
Initial value loaded into the transmit time slot counter at the trigger
edge of SCLKX when the synchronous pulse on port SYPX is active.
0…
1…
Only applicable for PCM highway configuration 8 MHz and 4 Mbit/s
0…
1…
Receive Clock Offset Shift
System Interface Channel Select
SICS
H
The delay T between the beginning of time slot 0 and the initial
edge of SCLKX (after SYPX goes active) is an even number in
the range of 0 to 1022 SCLKX cycles.
The delay T is an odd number in the range of 1 to 1023 SCLKX
cycles.
The delay T between the beginning of time slot 0 and the initial
edge of SCLKR (after SYPR goes active) is an even number in
the range of 0 to 1022 SCLKR cycles.
The delay T is an odd number in the range of 1 to 1023 SCLKR
cycles.
Received data is output on port RDO in the first channel
phase. Data line RDO is tristated in the second channel phase.
Data on pin XDI is sampled in the first channel phase only.
Data on XDI in the second channel phase is ignored.
Received data is output on port RDO in the second channel
phase. Data line RDO is tristated in the first channel phase.
Data on pin XDI is sampled in the second channel phase only.
Data on XDI in the first channel phase is ignored.
CRCI
XCRCI
204
RDIS
RCO2
RCO1
FALC-LH V1.3
RCO0
E1 Registers
0
PEB 2255
2000-07
(22)