peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 328

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

XDU…
XMB…
XLSC…
XPR…
Interrupt Status Register 2 (Read)
All bits are reset when ISR2 is read.
If bit PIC.VIS is set, interrupt statuses in ISR2 may be flagged although they are masked
via register IMR2. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
FAR…
Data Sheet
ISR2
FAR
7
Transmit Data Underrun
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO and no XME was
issued.
Note: Transmitter and XFIFO are reset and deactivated if this
Transmit Multiframe Begin
This bit is set with the beginning of a transmitted multiframe related to
the internal transmit line interface timing.
Transmit Line Status Change
XLSC is set with the rising edge of the bit FRS1.XLO or with any
change of bit FRS1.XLS.
The actual status of the transmit line monitor can be read from the
FRS1.XLS and FRS1.XLO.
Transmit Pool Ready
A data block of up to 32 bytes can be written to the transmit FIFO.
XPR enables the fastest access to XFIFO. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
The framer has reached synchronization. Set with the falling edge of
bit FSR0.LFA.
It is set also after alarm simulation is finished and the receiver is still
synchronous.
Frame Alignment Recovery
LFA
condition occurs. They are re-activated not before this
interrupt status register has been read. Thus, XDU should not
be masked via register IMR1.
MFAR
LMFA
328
AIS
LOS
RAR
FALC-LH V1.3
T1/J1 Registers
RA
0
PEB 2255
2000-07
(6A)