peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 77

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

If the FALC
passes the FALC
•
Figure 22
4.3.1.4
Transmit data stored in registers XS1-16 is transmitted in time slot 16 aligned to the
multiframe boundary. The signaling controller inserts the bit stream either on the transmit
line side or if external signaling is enabled on the transmit system side via pin function
XSIG.
Data sourced by the internal signaling controller overwrites the external signaling data.
If the FALC
passes the FALC
4.3.2
The received bit stream from pin XDI is optionally stored in the transmit elastic buffer.
The memory is organized as the receive elastic buffer. The functions are also equal to
the receive side. Programming of the transmit buffer size is done by SIC1.XBS1/0 :
• XBS1/0 = 00 : Bypass of the transmit elastic buffer
• XBS1/0 = 01 : one frame buffer or 256 bits
• XBS1/0 = 10 : two frame buffer or 512 bits
Data Sheet
Max. wander amplitude (peak-to-peak): 94 UI (1 UI = 488 ns )
average delay after performing a slip: 128 bits
Maximum of wander amplitude: 190 UI
average delay after performing a slip: 1 frame or 256 bits
SYPX
SCLKX
XDI
XSIG
T
FAS
NFAS
ABCD
Channel Associated Signaling CAS (E1, µP access mode)
Transmit Elastic Buffer (E1)
®
TS31
®
-LH is optioned for no signaling, the data stream from the system interface
A
-LH is optioned for no signaling, the data stream from the system interface
B
2.048 MHz Transmit Signaling Highway (E1)
C
= Time-Slot Offset (Register XC1/0)
= Frame Alignment Signal
= TS0 not containing the FAS word
= Signaling Bits for Time-Slot 1-30 of CAS Multiframe
T
D
®
®
-LH undisturbedly.
-LH undisturbedly.
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FAS / NFAS
TS0
TS1
A B C D
125 s
77
Functional Description E1
0 1 2 3 4 5 6 7
TS31
FALC-LH V1.3
A
B
C
PEB 2255
D
ITT10518
2000-07