peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 193

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Mask Register 0...5 (Read/Write)
Value after RESET: FF
IMR0...IMR5...
–
–
Note: After RESET, all interrupts are disabled.
Framer Mode Register 0 (Read/Write)
Value after RESET: 00
XC1... 0…
Data Sheet
FMR0
IMR0
IMR1
IMR2
IMR3
IMR4
IMR5
not displayed in the Interrupt Status Register if bit IPC.VIS is cleared
displayed in the Interrupt Status Register if bit IPC.VIS is set.
LLBSC
RME
FAR
XSP
XC1
LFA
ES
7
7
Each interrupt source can generate an interrupt signal on port INT
(characteristics of the output stage are defined via register IPC). A ‘1’
in a bit position of IMR0...5 sets the mask active for the interrupt status
in ISR0...3 and ISR5. Masked interrupt statuses neither generate a
signal on INT, nor are they visible in register GIS. Moreover, they are
Transmit Code
Serial code for the transmitter is independent to the receiver.
00... NRZ (optical interface)
01... CMI (1T2B + HDB3), (see FMR3 on
10... AMI (ternary or digital dual rail interface)
11... HDB3 Code (ternary or digital dual rail interface)
Interrupt Mask Register
RDO
SEC
XSN
RFS
FER
XC0
LFA
H
H
, FF
LMFA16
MFAR T400MS
T8MS
ALLS
H
CER
RC1
, FF
H
, FF
AIS16
RMB
XDU
RC0
AIS
H
, FF
193
H
EXTD
CASC
RA16
XMB
LOS
AIS
CRC4
LOS
CVE
ALM
API
page
SA6SC
XLSC
SLIP
RAR
RSN
FRS
210)
FALC-LH V1.3
XPR
RSP
RPF
EBE
SIM
RA
E1 Registers
0
0
PEB 2255
2000-07
(1A)
(14)
(15)
(16)
(17)
(18)
(19)