peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 266

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Common Configuration Register 1 (Read/Write)
Value after RESET: 00
SFLG…
BRM…
EDLX…
EITS…
ITF…
RFT1...0…
Data Sheet
CCR1
SFLG
7
If this bit is set, the closing flag of a preceding HDLC frame
simultaneously is used as the opening flag of the following frame.
0…
1…
0
1
Enable DL Bit Access via the Transmit FIFO
A one in this bit position enables the internal DL-bit access via the
receive/transmit FIFO of the signaling controller. FMR1.EDL has to be
cleared.
Enable Internal Time Slot 0-31 Signaling
0…
1…
Interframe Time Fill
Determines the idle (= no data to send) state of the transmit data
coming from the signaling controller.
0
1
RFIFO Threshold Level
The size of the accessible part of RFIFO can be determined by
programming these bits. The number of valid bytes after an RPF
interrupt is given in the following table:
Enable Shared Flags
BOM Receive Mode (significant in BOM mode only)
BRM
H
Shared flag function disabled
Shared flag function enabled
Internal signaling in time slots 0-31 defined via registers
RTR1...4 or TTR1...4 is disabled.
Internal signaling in time slots 0-31 defined via registers
RTR1...4 or TTR1...4 is enabled.
10 byte packets
Continuous reception
Continuous logical ‘1’ is output
Continuous FLAG sequences are output (‘01111110’ bit
patterns)
EDLX
EITS
266
ITF
RFT1
FALC-LH V1.3
T1/J1 Registers
RFT0
0
PEB 2255
2000-07
(09)