peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 256

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 5 (Read)
All bits are reset when ISR5 is read.
If bit IPC.VIS is set, interrupt statuses in ISR4 may be flagged although they are masked
via register IMR5. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
XSP…
XSN…
Global Interrupt Status Register (Read)
Value after RESET: 00
Version Status Register (Read)
VN7...0…
Data Sheet
ISR5
VSTR
GIS
XSP
VN7
7
7
7
Transmit Slip Positive
The frequency of the transmit clock is less than the frequency of the
transmit system interface working clock based on 2.048 MHz.
In 2-frame buffer mode a frame is skipped.
The frequency of the transmit clock is greater than the frequency of
the transmit system interface working clock based on 2.048 MHz.
In 2-frame buffer mode a frame is repeated
This status register points to pending interrupts sourced by ISR5 and
ISR3...ISR0.
Version Number of Chip
10
13
Transmit Slip Negative
XSN
VN6
H
H
…Version 1.1
…Version 1.3
H
VN5
ISR5
VN4
256
ISR3
VN3
ISR2
VN2
ISR1
VN1
FALC-LH V1.3
ISR0
VN0
E1 Registers
0
0
0
PEB 2255
2000-07
(6E)
(6F)
(6C)