peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 314

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Framer Receive Status Register 2 (Read)
ESC2…ESC0… Error Simulation Counter
Tested Alarms ESC2 … 0 =
LFA
LMFA
RRA (bit2 =0)
RRA (S-bit frame 12)
RRA (DL-pattern)
LOS
EBC (F12,F72)
EBC (only ESF)
AIS
FEC
CVC
CEC (only ESF)
SLPP
SLPN
XSLP
Some of these alarm indications are simulated only if the FALC
appropriate mode. At simulation steps 0, 3, 4, and 7 pending status flags are reset
automatically and clearing of the error counters and interrupt status registers ISR0...3
should be done. Incrementing the simulation counter should not be done at time intervals
shorter than 1.5 ms (F4, F12, F72) or 3 ms (ESF). Otherwise, reactions of initiated
simulations may occur at later steps.
Data Sheet
FRS2
ESC2
7
This three-bit counter is incremented by setting bit FMR0.SIM. The
state of the counter determines the function to be tested:
For complete checking of the alarm indications, eight simulation steps
are necessary (FRS2.ESC = 0 after a complete simulation).
ESC1
ESC0
0
314
1
x
x
x
x
x
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
3
®
-LH is configured in the
4
FALC-LH V1.3
T1/J1 Registers
5
x
x
x
x
x
x
x
0
PEB 2255
6
x
x
x
x
x
x
x
x
x
2000-07
(4E)
7