peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 274

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Framer Mode Register 1 (Read/Write)
Value after RESET: 00
CTM…
SIGM…
Note: Bit FMR5.EIBR has also to be set, if bit-robbing mode is to be used.
EDL…
PMOD…
Data Sheet
FMR1
CTM
7
simulation steps are necessary (FRS2.ESC2...0 = 0 after a complete
simulation).
Channel Translation Mode
0…
1…
See
0…
1…
Enable DL-Bit Access via Register XDL1...3
Only applicable in F4, F24 or F72 frame format.
0…
1…
PCM Mode
For T1/J1 applications this bit must be set high. Switching into T1/J1
mode the device needs up to 10
clocking.
0…
1…
Select Signaling Mode
SIGM
H
Table 26
Channel translation mode 0
Channel translation mode 1
Normal operation (no bit-robbing).
CAS Bit-robbing mode selected
Normal operation. The DL-bits are taken from system highway
or if enabled via CCR1.EDLX from the XFIFO of the signaling
controller.
DL-bit register access. The DL-bit information is taken from the
registers XDL1...3 and overwrites the DL-bits received at the
system highway (pin XDI) or the internal XFIFO of the signaling
controller. However, transmitting contents of registers XDL1...3
is disabled if transparent mode is enabled (FMR4.TM).
PCM 30 or E1 mode.
PCM 24 or T1/J1 mode.
EDL
on page
PMOD
113
274
CRC
for details.
ECM
s to settle up to the internal
IMOD
FALC-LH V1.3
T1/J1 Registers
XAIS
0
PEB 2255
2000-07
(1B)