peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 331

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

RSN…
RSP…
Interrupt Status Register 4 (Read)
All bits are reset when ISR5 is read.
If bit IPC.VIS is set, interrupt statuses in ISR5 may be flagged although they are masked
via register IMR5. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
XSP…
Data Sheet
ISR5
XSP
7
The LLBSC bit is also set, if the current detection status is left, i.e., if
the bit error rate exceeds 1/100.
The actual detection status can be read from the FRS1.LLBAD and
FRS1.LLBDD, respectively.
PRBS Status Change
LCR1.EPRM=1: With any change of state of the PRBS synchronizer
this bit is set. The current status of the PRBS synchronizer is
indicated in FRS1.LLBAD.
The frequency of the receive route clock is greater than the frequency
of the receive system interface working clock based on 1.544 MHz. It
is set during alarm simulation.
In 2-frame buffer mode a frame is skipped.
The frequency of the receive route clock is less than the frequency of
the receive system interface working clock based on 1.544 MHz. It is
set during alarm simulation.
In 2-frame buffer mode a frame is repeated.
Transmit Slip Positive
The frequency of the transmit clock is less than the frequency of the
transmit system interface working clock based on 1.544 MHz. After a
slip has performed writing of register XC1 is not necessary.
In 2-frame buffer mode a frame is repeated.
Receive Slip Negative
Receive Slip Positive
XSN
331
FALC-LH V1.3
T1/J1 Registers
0
PEB 2255
2000-07
(6C)