peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 33

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 3
Pin No.
66
75
76
77
78
60
Data Sheet
Symbol
FSC
CLK16M
CLK12M
CLK8M
CLKX
SYNC
Pin Definitions - Clock Generation (cont’d)
Input (I)
Output (O)
Supply (S)
O
O
O
O
O
I
Function
8 kHz Frame Synchronization Pulse
is output on this pin. The synchronization pulse
is active low for one cycle (pulse width = 488 ns)
and derived from the clock supplied on pin
CLK16M.
System Clock 16.384 MHz
Buffered XTAL1 clock (LIM3.CSC=1) or jitter
attenuated clock (LIM3.CSC=0, if crystal-less
jitter attenuation is used).
System Clock
16.384 MHz (E1)/12.384 MHz (T1/J1)
Buffered XTAL3 clock (LIM3.CSC=1) or jitter
attenuated clock (LIM3.CSC=0, if crystal-less
jitter attenuation is used).
System Clock 8.192 MHz
Clock derived from CLK16M reference.
System Clock Output
Output frequencies are 2.048 MHz or 4.096
MHz, inverted or non-inverted. The clock is
derived from CLK16M, frequency and polarity in
relation to FSC are selected by setting of
LIM0.SCL1...0.
Clock Synchronization
If a clock is detected at the SYNC pin, the
FALC
2.048 or 1.544-MHz (T1/J1) clock if in master
mode or if signal is lost in slave mode. This pin
has to be connected to V
supplied.
33
®
-LH synchronizes to this 2.048-MHz (E1)/
SS
, if no clock is
Pin Descriptions
FALC-LH V1.3
PEB 2255
2000-07