MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet
MMC2114CFCAG33
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... Freescale Semiconductor, Inc. M•CORE Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MMC2114 MMC2113 MMC2112 Advance Information MMC2114/D Rev. 1, 4/2002 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. MMC2114 MMC2113 MMC2112 Advance Information To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www ...
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... Freescale Semiconductor, Inc. Advance Information Revision Date Level March, 2002 N/A April, 2002 1.0 Advance Information 4 Revision History Description Original release Figure 4-4. Chip Identification Register (CIR) Corrrected reset condition for bits 11 and 8 20.9.3 Show Strobe (SHS) — Corrected description in first paragraph 23 ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 45 Section 2. System Memory Map . . . . . . . . . . . . . . . . . . . 53 Section 3. Signal Description Section 4. Chip Configuration Module (CCM 121 Section 5. Reset Controller Module 139 Section 6. Power Management . . . . . . . . . . . . . . . . . . . 155 Section 7. M•CORE M210 Central Processor Section 8 ...
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... Freescale Semiconductor, Inc. List of Sections Section 17. Serial Communications Interface Section 18. Serial Peripheral Interface Section 19. Queued Analog-to-Digital Section 20. External Bus Interface Module (EBI 527 Section 21. Chip Select Module . . . . . . . . . . . . . . . . . . . 547 Section 22. JTAG Test Access Port and OnCE . . . . . . 559 Section 23. Preliminary Electrical Specifications . . . . 611 Section 24 ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.4 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 1 ...
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... Freescale Semiconductor, Inc. Table of Contents 3.5 3.5.1 3.5.1.1 3.5.1.2 3.5.2 3.5.2.1 3.5.2.2 3.5.2.3 3.5.2.4 3.5.3 3.5.3.1 3.5.3.2 3.5.3.3 3.5.3.4 3.5.3.5 3.5.3.6 3.5.3.7 3.5.3.8 3.5.3.9 3.5.3.10 3.5.3.11 3.5.4 3.5.4.1 3.5.4.2 3.5.4.3 3.5.5 3.5.5.1 3.5.5.2 3.5.5.3 3.5.5.4 3.5.6 3.5.6.1 3.5.6.2 3.5.7 Advance Information 8 Signal Descriptions ...
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... Freescale Semiconductor, Inc. 3.5.8 3.5.8.1 3.5.8.2 3.5.8.3 3.5.8.4 3.5.9 3.5.9.1 3.5.9.2 3.5.9.3 3.5.9.4 3.5.9.5 3.5.9.6 3.5.10 3.5.11 3.5.11.1 3.5.11.2 3.5.11.3 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.3.1 4.7.3.2 4.7.3.3 4.7.3.4 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Table of Contents 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.9 4.10 5.1 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.6 5.6.1 5.6.2 5.7 5.7.1 5.7.1.1 5.7.1.2 5.7.1.3 5.7.1.4 5.7.1.5 5.7.1.6 5.7.1.7 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 Advance Information 10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Reset Configuration ...
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... Freescale Semiconductor, Inc. 5.7.3 5.7.3.1 5.7.3.2 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.4.9 6.4.10 6.4.11 6.4.12 6.4.13 6.4.14 6.5 7.1 7.2 7.3 7.4 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Table of Contents 7.5 7.6 7.7 7.8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.7.2.1 8.7.2.2 8.7.2.3 8.7.2.4 8.7.2.5 8.7.2.6 8.7.2.7 8.7.2.8 8.7.2.9 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.4.1 8.8.4.2 8.8.4.3 8.8.5 Advance Information 12 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Data Format Summary ...
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... Freescale Semiconductor, Inc. Section 9. Static Random Access Memory (SRAM) 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.7.1 10.7.1.1 10.7.1.2 10.7.1.3 10.7.1.4 10.7.1.5 10.7.2 10.7.2.1 10.7.2.2 10.7.2.3 10.7.2.4 10.7.2.5 10.7.2.6 10.7.2.7 10.7.2.8 10.7.2.9 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Table of Contents 10.8 10.8.1 10.8.2 10.8.3 10.8.3.1 10.8.3.2 10.8.3.3 10.8.3.4 10.8.4 10.8.5 10.8.6 10.8.7 10.9 10.9.1 10.9.2 10.10 Resets 240 10.11 Interrupts 240 11.1 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.4.1 11.4.4.2 11.5 11.6 11.6.1 11.6.2 11.6.3 11 ...
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... Freescale Semiconductor, Inc. 11.7 11.7.1 11.7.2 11.7.2.1 11.7.2.2 11.7.2.3 11.7.2.4 11.8 11.8.1 11.8.2 11.8.3 11.8.3.1 11.8.3.2 11.8.4 11.8.4.1 11.8.4.2 11.8.5 11.8.6 11.8.6.1 11.8.6.2 11.8.6.3 11.8.6.4 11.9 11.10 Interrupts 269 12.1 12.2 12.3 12.4 12.4.1 12.4.2 12.4.2.1 12.4.2.2 12.4.2.3 12.4.2.4 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Table of Contents 12.4.2.5 12.4.2.6 12.5 12.5.1 12.5.2 12.6 13.1 13.2 13.3 13.3.1 13.3.2 13.4 13.5 13.5.1 13.5.2 13.5.2.1 13.5.2.2 13.5.2.3 13.5.2.4 13.5.2.5 13.5.2.6 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.4 14.5 14.6 Advance Information 16 Port C/D Pin Assignment Register . . . . . . . . . . . . . . . . . 279 Port E Pin Assignment Register ...
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... Freescale Semiconductor, Inc. 14.6.1 14.6.2 14.6.2.1 14.6.2.2 14.6.2.3 14.6.2.4 Section 15. Programmable Interrupt Timer Modules 15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.5 15.6 15.6.1 15.6.2 15.6.2.1 15.6.2.2 15.6.2.3 15.7 15.7.1 15.7.2 15.7.3 15.8 16.1 16.2 16.3 16.4 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Table of Contents 16.5 16.5.1 16.5.2 16.5.3 16.5.4 16.5.5 16.6 16.6.1 16.6.2 16.7 16.7.1 16.7.2 16.7.3 16.7.4 16.7.5 16.7.6 16.7.7 16.7.8 16.7.9 16.7.10 Timer Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . 333 16.7.11 Timer System Control Register 334 16.7.12 Timer Flag Register 336 16 ...
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... Freescale Semiconductor, Inc. 16.8.5 16.9 16.10 Interrupts 351 16.10.1 Timer Channel Interrupts (CxF 351 16.10.2 Pulse Accumulator Overflow (PAOVF 352 16.10.3 Pulse Accumulator Input (PAIF 352 16.10.4 Timer Overflow (TOF 352 Section 17. Serial Communications Interface Modules 17.1 17.2 17.3 17.4 17.5 17 ...
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... Freescale Semiconductor, Inc. Table of Contents 17.11.2 Transmitting a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 17.11.3 Break Frames 380 17.11.4 Idle Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 17.12 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 17.12.1 Frame Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 17.12.2 Receiving a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 17.12.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 17.12.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 17.12.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 17 ...
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... Freescale Semiconductor, Inc. 18.7 18.7.1 18.7.2 18.7.3 18.7.4 18.7.5 18.7.6 18.7.7 18.7.8 18.8 18.8.1 18.8.2 18.8.3 18.8.3.1 18.8.3.2 18.8.4 18.8.5 18.8.6 18.8.7 18.8.7.1 18.8.7.2 18.8.8 18.8.8.1 18.8.8.2 18.8.8.3 18.9 18.10 Interrupts 424 18.10.1 Mode Fault (MODF) Flag . . . . . . . . . . . . . . . . . . . . . . . . . . 424 18.10.2 SPI Interrupt Flag (SPIF 424 19 ...
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... Freescale Semiconductor, Inc. Table of Contents 19.5 19.5.1 19.5.2 19.6 19.6.1 19.6.1.1 19.6.1.2 19.6.2 19.6.2.1 19.6.2.2 19.6.3 19.6.4 19.6.5 19.6.6 19.6.7 19.6.8 19.7 19.8 19.8.1 19.8.2 19.8.3 19.8.4 19.8.5 19.8.5.1 19.8.5.2 19.8.5.3 19.8.6 19.8.6.1 19.8.6.2 19.8.7 19.8.8 19.8.8.1 19.8.8.2 19.8.8.3 Advance Information 22 Modes of Operation ...
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... Freescale Semiconductor, Inc. 19.9 19.9.1 19.9.2 19.9.2.1 19.9.2.2 19.9.3 19.9.3.1 19.9.3.2 19.9.3.3 19.9.3.4 19.9.3.5 19.9.3.6 19.9.3.7 19.9.3.8 19.9.3.9 19.10 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478 19.10.1 Queue Priority Timing Examples . . . . . . . . . . . . . . . . . . . . 478 19.10.1.1 19.10.1.2 19.10.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 19.10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 19.10.4 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 19 ...
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... Freescale Semiconductor, Inc. Table of Contents 19.11 Pin Connection Considerations . . . . . . . . . . . . . . . . . . . . . . .509 19.11.1 Analog Reference Pins .509 19.11.2 Analog Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 19.11.3 Conversion Timing Schemes . . . . . . . . . . . . . . . . . . . . . . .512 19.11.4 Analog Supply Filtering and Grounding . . . . . . . . . . . . . . . 515 19.11.5 Accommodating Positive/Negative Stress Conditions . . . .517 19.11.6 Analog Input Considerations . . . . . . . . . . . . . . . . . . . . . . .519 19 ...
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... Freescale Semiconductor, Inc. 20.7 20.7.1 20.7.1.1 20.7.1.2 20.7.1.3 20.7.2 20.7.2.1 20.7.2.2 20.7.2.3 20.8 20.8.1 20.8.2 20.9 20.9.1 20.9.2 20.9.3 20.9.4 20.9.5 20.10 Bus Monitor 545 20.11 Interrupts 545 21.1 21.2 21.3 21.4 21.5 21.6 21.6.1 21.6.2 21.7 21.8 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Table of Contents 22.1 22.2 22.3 22.3.1 22.3.2 22.3.3 22.3.4 22.3.5 22.3.6 22.4 22.5 22.5.1 22.5.2 22.5.3 22.5.4 22.5.5 22.5.6 22.5.7 22.6 22.7 22.8 22.9 22.10 Non-Scan Chain Operation 573 22.11 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 22.12 Low-Level TAP (OnCE) Module . . . . . . . . . . . . . . . . . . . . . . .579 22 ...
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... Freescale Semiconductor, Inc. 22.14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 22.14.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 22.14.2 OnCE Controller and Serial Interface 584 22.14.3 OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 22.14.3.1 22.14.3.2 22.14.3.3 22.14.3.4 22.14.3.5 22.14.3.6 22.14.3.7 22.14.4 OnCE Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . 587 22.14.4.1 22.14.4.2 22.14.4.3 22.14.5 OnCE Decoder (ODEC 596 22 ...
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... Freescale Semiconductor, Inc. Table of Contents 22.14.12.5 Processor Status Register . . . . . . . . . . . . . . . . . . . . . . .605 22.14.13 Instruction Address FIFO Buffer (PC FIFO 606 22.14.14 Reserved Test Control Registers . . . . . . . . . . . . . . . . . . . . 607 22.14.15 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 22.14.16 OnCE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 22.14.17 Target Site Debug System Requirements . . . . . . . . . . . . . 608 22.14.18 Interface Connector for JTAG/OnCE Serial Port . . . . . . . . 608 23 ...
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... Freescale Semiconductor, Inc. 24.8 24.9 25.1 25.2 25.3 A.1 A.2 A.3 A.4 A.4.1 A.4.2 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, 100-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . . 644 196-Ball MAPBGA Mechanical Drawing 645 Section 25. Ordering Information Contents ...
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... Freescale Semiconductor, Inc. Table of Contents Advance Information 30 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 Figure 1-1 2-1 2-2 2-3 2-4 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 5-1 5-2 5-3 5-4 7-1 7-2 7-3 7-4 8-1 8-2 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. List of Figures Figure 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 Fast Interrupt Pending Register (FIPR 190 8-11 Priority Level Select Registers (PLSR0–PLSR39 .191 10-1 SGFM Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 208 10-2 SGFM Array Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 10-3 SGFM Module Configuration Register (SGFMCR .213 10-4 SGFM Clock Divider Register (SGFMCLKD) ...
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... Freescale Semiconductor, Inc. Figure 11-7 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 11-8 Crystal Oscillator Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12-1 Ports Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 272 12-2 Port Output Data Registers (PORTx .275 12-3 Port Data Direction Registers (DDRx .276 12-4 Port Pin Data/Set Data Registers (PORTxP/SETx 277 12-5 Port Clear Output Data Registers (CLRx) ...
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... Freescale Semiconductor, Inc. List of Figures Figure 16-3 Timer Compare Force Register (TIMCFORC 325 16-4 Timer Output Compare 3 Mask Register (TIMOC3M 326 16-5 Timer Output Compare 3 Data Register (TIMOC3D 327 16-6 Timer Counter Register High (TIMCNTH 328 16-7 Timer Counter Register Low (TIMCNTL 328 16-8 Timer System Control Register (TIMSCR1) ...
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... Freescale Semiconductor, Inc. Figure 17-10 SCI Pullup and Reduced Drive Register (SCIPURD 371 17-11 SCI Port Data Register (SCIPORT 372 17-12 SCI Data Direction Register (SCIDDR 373 17-13 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 17-14 Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 17-15 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 381 17-16 Receiver Data Sampling ...
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... Freescale Semiconductor, Inc. List of Figures Figure 19-5 QADC Port QA Data Register (PORTQA 439 19-6 QADC Port QB Data Register (PORTQB 439 19-7 QADC Port QA Data Direction Register (DDRQA) 19-8 QADC Control Register 0 (QACR0 442 19-9 QADC Control Register 1 (QACR1 445 19-10 QADC Control Register 2 (QACR2 448 19-11 QADC Status Register 0 (QASR0) ...
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... Freescale Semiconductor, Inc. Figure 19-40 CCW Freeze Situation .491 19-41 CCW Freeze Situation .491 19-42 QADC Clock Subsystem Functions . . . . . . . . . . . . . . . . . . . . 503 19-43 QADC Conversion Queue Operation . . . . . . . . . . . . . . . . . . . 506 19-44 Equivalent Analog Input Circuitry . . . . . . . . . . . . . . . . . . . . . . 510 19-45 Errors Resulting from Clipping . . . . . . . . . . . . . . . . . . . . . . . . 511 19-46 External Positive Edge Trigger Mode Timing with Pause 512 19-47 Gated Mode, Single Scan Timing ...
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... Freescale Semiconductor, Inc. List of Figures Figure 22-8 OnCE Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 22-9 OnCE Command Register (OCMR 588 22-10 OnCE Control Register (OCR 590 22-11 OnCE Status Register (OSR 594 22-12 OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . . . . 596 22-13 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . 599 22-14 CPU Scan Chain Register (CPUSCR) ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 Table 1-1 2-1 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 Boot Device Selection 136 4-11 Output Pad Driver Strength Selection .137 4-12 Clock Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ...
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... Freescale Semiconductor, Inc. List of Tables Table 8-1 8-2 8-3 8-4 8-5 8-6 10-1 SGFM Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 10-2 SGFM Register Address Map 212 10-3 Register Bank Select Decoding . . . . . . . . . . . . . . . . . . . . . . .215 10-4 Security States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 10-5 SGFMCMD User Mode Commands . . . . . . . . . . . . . . . . . . . . 226 10-6 FLASH User Mode Commands . . . . . . . . . . . . . . . . . . . . . . .234 10-7 SGFM Interrupt Sources ...
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... Freescale Semiconductor, Inc. Table 15-1 Programmable Interrupt Timer Modules Memory Map . . . . . . 308 15-2 Prescaler Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 15-3 PIT Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 16-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 16-2 Timer Modules Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 323 16-3 Output Compare Action Selection . . . . . . . . . . . . . . . . . . . . . 331 16-4 Input Capture Edge Selection 332 16-5 Prescaler Selection ...
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... Freescale Semiconductor, Inc. List of Tables Table 19-3 Prescaler f 19-4 Queue 1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 19-5 Queue 2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 19-6 CCW Pause Bit Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 19-7 Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .458 19-8 Input Sample Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465 19-9 Non-Multiplexed Channel Assignments 19-10 Multiplexed Channel Assignments 19-11 Analog Input Channels ...
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... Freescale Semiconductor, Inc. Table 23-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 613 23-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 23-3 ESD Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . .615 23-4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 616 23-5 PLL Electrical Specifications 618 23-6 QADC Absolute Maximum Ratings 620 23-7 QADC Electrical Specifications (Operating .621 23-8 QADC Conversion Specifications (Operating 622 23-9 SGFM FLASH Program and Erase Characteristics ...
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... Freescale Semiconductor, Inc. List of Tables Advance Information 44 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 List of Tables For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 1.1 Contents 1.2 1.3 1.4 1.2 Introduction The MMC2114, MMC2113, and MMC2112 are members of a family of general-purpose microcontrollers (MCU) based on the M•CORE M210 central processor unit (CPU). These are low-voltage devices that operate between 2.7 volts and 3 ...
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... Freescale Semiconductor, Inc. General Description Device MMC2112 MMC2113 MMC2114 1. See NOTE: The MMC2113 may contain more than 8K of internal SRAM, but only the 8K range from 0x0080_0000 to 0x0080_1fff is tested and guaranteed to be operational recommended that internal SRAM outside this range not be used. Accesses to SRAM outside this range terminate without a transfer error exception ...
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... Freescale Semiconductor, Inc. • • • MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, – Enhanced security feature prevents unauthorized access to contents of FLASH (protects company IP) – Single supply operation (no need for separate, high voltage program/erase supply) ...
Page 48
... Freescale Semiconductor, Inc. General Description • • Advance Information 48 Two timers: – Four 16-bit input capture/output compare channels – 16-bit architecture – 16-bit pulse accumulator – Pulse widths variable from microseconds to seconds – Eight selectable prescalers – Toggle-on-overflow feature for pulse-width modulation Queued analog-to-digital converter (QADC): – ...
Page 49
... Freescale Semiconductor, Inc. • • • • MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, Interrupt controller: – interrupt sources – 32 unique programmable priority levels for each interrupt source – Independent enable/disable of pending interrupts based on priority level – ...
Page 50
... Freescale Semiconductor, Inc. General Description • • • • • Advance Information 50 Phase-lock loop (PLL): – Reference crystal from MHz – Low-power modes supported – Separate clock-out signal Integrated low-voltage detector (LVD): – Can be enabled and disabled under software control – Sets flag when V ...
Page 51
... Freescale Semiconductor, Inc. • • 1.4 Block Diagram The basic structure of these devices is shown in MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, External bus interface: – Provides for direct support of asynchronous random-access memory (RAM), read-only memory (ROM), FLASH, and memory mapped peripherals – ...
Page 52
... Freescale Semiconductor, Inc. General Description JTAG TAP OnCE CPU INTERRUPT CONTROLLER EDGE INT[7:0] PORT TIM1 TIM2 Advance Information 52 SRAM 8 KBYTES (MMC2113) 32 KBYTES (MMC2112/4) CPU BUS IPBUS INTERFACE PROGRAMMABLE INTERVAL TIMER 1 PROGRAMMABLE OSC/PLL INTERVAL TIMER 2 WATCHDOG TIMER IPBUS SCI1 SCI2 Figure 1-1. Block Diagram MMC2114 • ...
Page 53
... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 2.1 Contents 2.2 2.3 2.4 2.2 Introduction The address maps, shown in include: • • • • MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 2. System Memory Map Introduction ...
Page 54
... Freescale Semiconductor, Inc. System Memory Map 2.3 Address Map Advance Information 54 0xffff_ffff EXTERNAL MEMORY 0x8000_0000 0x00d0_002f 0x00c0_0000 0x0080_7fff 0x0080_0000 0x0000_0000 Figure 2-1. MMC2112 Address Map 0xffff_ffff EXTERNAL MEMORY 0x8000_0000 0x00d0_002f 0x00c0_0000 0x0080_1fff 0x0080_0000 0x0001_ffff 0x0000_0000 Figure 2-2. MMC2113 Address Map MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
Page 55
... Freescale Semiconductor, Inc. NOTE: The MMC2113 may contain more than 8K of internal SRAM, but only the 8K range from 0x0080_0000 to 0x0080_1fff is tested and guaranteed to be operational recommended that internal SRAM outside this range not be used. Accesses to SRAM outside this range terminate without a transfer error exception. MMC2114 • ...
Page 56
... Freescale Semiconductor, Inc. System Memory Map Base Address 0x00c0_0000 0x00c1_0000 0x00c2_0000 0x00c3_0000 0x00c4_0000 0x00c5_0000 0x00c6_0000 0x00c7_0000 0x00c8_0000 0x00c9_0000 0x00ca_0000 0x00cb_0000 0x00cc_0000 0x00cd_0000 0x00ce_0000 0x00cf_0000 0x00d0_0000 0x8000_0000 1. See module sections for details of how much of each block is being decoded. Accesses to addresses outside the module memory maps (and also the reserved area 0x00d1_0000– ...
Page 57
... Freescale Semiconductor, Inc. 2.4 Register Map Address Register Name Ports (PORTS) 0x00c0_0000 Port A Output Data Read: Register (PORTA) See page 275. Reset: 0x00c0_0001 Port B Output Data Read: Register (PORTB) See page 275. Reset: 0x00c0_0002 Port C Output Data Read: Register (PORTC) See page 275. ...
Page 58
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c0_0007 Port H Output Data Register (PORTH) See page 275. 0x00c0_0008 Port I Output Data Register (PORTI) See page 275. 0x00c0_0009 Reserved 0x00c0_000b 0x00c0_000c Port A Data Direction Register (DDRA) See page 276. 0x00c0_000d Port B Data Direction Register (DDRB) See page 276 ...
Page 59
... Freescale Semiconductor, Inc. Address Register Name 0x00c0_0011 Port F Data Direction Read: Register (DDRF) See page 276. Reset: 0x00c0_0012 Port G Data Direction Read: Register (DDRG) See page 276. Reset: 0x00c0_0013 Port H Data Direction Read: Register (DDRH) See page 276. Reset: 0x00c0_0014 Port I Data Direction ...
Page 60
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c0_001b Port D Pin Data/Set Data Register (PORTDP/SETD) See page 277. 0x00c0_001c Port E Pin Data/Set Data Register (PORTEP/SETE) See page 277. 0x00c0_001d Port F Pin Data/Set Data Register (PORTFP/SETF) See page 277. 0x00c0_001e Port G Pin Data/Set ...
Page 61
... Freescale Semiconductor, Inc. Address Register Name 0x00c0_0025 Port B Clear Output Read: Data Register (CLRB) See page 278. Reset: 0x00c0_0026 Port C Clear Output Read: Data Register (CLRC) See page 278. Reset: 0x00c0_0027 Port D Clear Output Read: Data Register (CLRD) See page 278. ...
Page 62
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c0_002c Port I Clear Output Data Register (CLRI) See page 278. 0x00c0_002d Reserved 0x00c0_002f 0x00c0_0030 Port C/D Pin Assignment Register (PCDPAR) See page 279. 0x00c0_0031 Port E Pin Assignment Register (PEPAR) See page 280. ...
Page 63
... Freescale Semiconductor, Inc. Address Register Name Chip Configuration Module (CCM) 0x00c1_0000 Chip Configuration Read: 0x00c1_0001 Register (CCR) See page 126. Reset: Read: Reset: 0x00c1_0002 Reserved 0x00c1_0003 Reserved 0x00c1_0004 Reset Configuration Read: 0x00c1_0005 Register (RCON) See page 129. Reset: Read: Reset Current pin state U = Unaffected Figure 2-4 ...
Page 64
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c1_0006 Chip Identification 0x00c1_0007 Register (CIR) See page 131. 0x00c1_0008 Chip Test Register 0x00c1_0009 (CTR) See page 132. 0x00c1_000a Reserved 0x00c1_000b 0x00c1_000c Unimplemented 0x00c1_000f 0x00c1_0010 Unimplemented 0x00c1_ffff P = Current pin state U = Unaffected Figure 2-4. Register Summary (Sheet 8 of 37) ...
Page 65
... Freescale Semiconductor, Inc. Address Register Name Chip Selects (CS) 0x00c2_0000 Chip Select Control Read: 0x00c2_0001 Register 0 (CSCR0) See page 551. Reset: Read: Reset: 0x00c2_0002 Chip Select Control Read: 0x00c2_0003 Register 1 (CSCR1) See page 552. Reset: Read: Reset: 0x00c2_0004 Chip Select Control Read: ...
Page 66
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c2_0006 Chip Select Control 0x00c2_0007 Register 3 (CSCR3) See page 553. 0x00c2_0008 Unimplemented 0x00c2_ffff Clocks (CLOCK) 0x00c3_0000 Synthesizer Control 0x00c3_0001 Register (SYNCR) See page 250. 0x00c3_0002 Synthesizer Status Register (SYNSR) See page 253. ...
Page 67
... Freescale Semiconductor, Inc. Address Register Name 0x00c3_0003 Synthesizer Test Register Read: (SYNTR) See page 256. Reset: 0x00c3_0004 Synthesizer Test Read: 0x00c3_0005 Register 2 (SYNTR2) 0x00c3_0006 See page 257. 0x00c3_0007 Reset: Read: Reset: Read: Reset: Read: Reset: 0x00c3_0008 Unimplemented 0x00c3_ffff Reset (RESET) 0x00c4_0000 ...
Page 68
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c4_0001 Reset Status Register (RSR) See page 143. 0x00c4_0002 Reset Test Register (RTR) 0x00c4_0003 Reserved 0x00c4_0004 Unimplemented 0x00c4_ffff Interrupt Controller (INTC) 0x00c5_0000 Interrupt Control Register 0x00c5_0001 (ICR) See page 181. 0x00c5_0002 Interrupt Status Register ...
Page 69
... Freescale Semiconductor, Inc. Address Register Name 0x00c5_0004 Interrupt Force Register Read: 0x00c5_0005 High (IFRH) 0x00c5_0006 See page 184. 0x00c5_0007 Reset: Read: Reset: Read: Reset: Read: Reset: 0x00c5_0008 Interrupt Force Register Read: 0x00c5_0009 Low (IFRL) 0x00c5_000a See page 185. 0x00c5_000b Reset: Read: ...
Page 70
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c5_000c Interrupt Pending Register 0x00c5_000d (IPR) 0x00c5_000e See page 186. 0x00c5_000f 0x00c5_0010 Normal Interrupt Enable 0x00c5_0011 Register (NIER) 0x00c5_0012 See page 187. 0x00c5_0013 P = Current pin state U = Unaffected Figure 2-4. Register Summary (Sheet 14 of 37) ...
Page 71
... Freescale Semiconductor, Inc. Address Register Name 0x00c5_0014 Normal Interrupt Pending Read: 0x00c5_0015 Register (NIPR) 0x00c5_0016 See page 188. 0x00c5_0017 Reset: Read: Reset: Read: Reset: Read: Reset: 0x00c5_0018 Fast Interrupt Enable Read: 0x00c5_0019 Register (FIER) 0x00c5_001a See page 189. 0x00c5_001b Reset: Read: ...
Page 72
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c5_001c Fast Interrupt Pending 0x00c5_001d Register (FIPR) 0x00c5_001e See page 190. 0x00c5_001f 0x00c5_0040 Priority Level Select Registers 0x00c5_0067 (PLSR39–PLSR0) See page 191. 0x00c5_0068 Unimplemented 0x00c5_007f 0x00c5_0080 Unimplemented 0x00c5_ffff P = Current pin state U = Unaffected Figure 2-4 ...
Page 73
... Freescale Semiconductor, Inc. Address Register Name Edge Port (EPORT) 0x00c6_0000 EPORT Pin Assignment Read: 0x00c6_0001 Register (EPPAR) See page 288. Reset: Read: Reset: 0x00c6_0002 EPORT Data Direction Read: Register (EPDDR) See page 290. Reset: 0x00c6_0003 EPORT Port Interrupt Read: Enable Register (EPIER) See page 291 ...
Page 74
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c6_0008 Unimplemented 0x00c6_ffff Watchdog Timer (WDT) 0x00c7_0000 Watchdog Control 0x00c7_0001 Register (WCR) See page 299. 0x00c7_0002 Watchdog Modulus 0x00c7_0003 Register (WMR) See page 301. 0x00c7_0004 Watchdog Count Register 0x00c7_0005 (WCNTR) See page 302. ...
Page 75
... Freescale Semiconductor, Inc. Address Register Name 0x00c7_0006 Watchdog Service Read: 0x00c7_0007 Register (WSR) See page 303. Reset: Read: Reset: 0x00c7_0008 Unimplemented 0x00c7_ffff Programmable Interrupt Timer 1 (PIT1) and Programming Interrupt Timer 2 (PIT2) Note: Addresses for PIT1 are at 0x00c8_#### and addresses for PIT2 are at 0x00c9_####. ...
Page 76
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c8_0004 PIT Count Register 0x00c8_0005 (PCNTR) 0x00c9_0004 See page 313. 0x00c9_0005 0x00c8_0006 Unimplemented 0x00c8_0007 0x00ca_0008 Unimplemented 0x00ca_ffff Queued Analog-to-Digital Converter (QADC) 0x00ca_0000 QADC Module 0x00ca_0001 Configuration Register (QADCMCR) See page 437. 0x00ca_0002 ...
Page 77
... Freescale Semiconductor, Inc. Address Register Name 0x00ca_0004 Reserved 0x00ca_0005 0x00ca_0006 QADC Port A Data Read: Register (PORTQA) See page 439. Reset: 0x00ca_0007 QADC Port B Data Read: Register (PORTQB) See page 439. Reset: 0x00ca_0008 QADC Port A Data Read: Direction Register (DDRQA) See page 441. ...
Page 78
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00ca_000c QADC Control Register 1 0x00ca_000d (QACR1) See page 445. 0x00ca_000e QADC Control Register 2 0x00ca_000f (QACR2) See page 448. 0x00ca_0010 QADC Status Register 0 0x00ca_0011 (QASR0) See page 453 Current pin state U = Unaffected Figure 2-4. Register Summary (Sheet 22 of 37) ...
Page 79
... Freescale Semiconductor, Inc. Address Register Name 0x00ca_0012 QADC Status Register 1 Read: 0x00ca_0013 (QASR1) See page 462. Reset: Read: Reset: 0x00ca_0014 Reserved 0x00ca_01ff 0x00ca_0200 Conversion Command Read: 0x00ca_027e Word Register (CCW0–CCW63) See page 464. Reset: Read: Reset: 0x00ca_0280 Right-Justified Unsigned Read: ...
Page 80
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00ca_0300 Left-Justified Signed 0x00ca_037e Result Register (LJSRR0–LJSRR63) See page 469. 0x00ca_0380 Left-Justified Unsigned 0x00ca_03fe Result Register (LJURR0–LJURR63) See page 470. 0x00ca_0400 Unimplemented 0x00ca_ffff Serial Peripheral Interface (SPI) 0x00cb_0000 SPI Control Register 1 (SPICR1) See page 402 ...
Page 81
... Freescale Semiconductor, Inc. Address Register Name 0x00cb_0002 SPI Baud Rate Register Read: (SPIBR) See page 406. Reset: 0x00cb_0003 SPI Status Register Read: (SPISR) See page 408. Reset: 0x00cb_0004 Reserved 0x00cb_0005 SPI Data Register Read: (SPIDR) See page 409. Reset: 0x00cb_0006 SPI Pullup and Reduced ...
Page 82
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00cb_0010 Unimplemented 0x00cb_ffff Serial Communications Interface 1 (SCI1) and Serial Communications Interface 2 (SCI2) Note: Addresses for SCI1 are at 0x00cc_#### and addresses for SCI2 are at 0x00cd_####. 0x00cc_0000 SCI Baud Rate 0x00cd_0000 Register High (SCIBDH) See page 360 ...
Page 83
... Freescale Semiconductor, Inc. Address Register Name 0x00cc_0006 SCI Data Register High Read: 0x00cd_0006 (SCIDRH) See page 370. Reset: 0x00cc_0007 SCI Data Register Low Read: 0x00cd_0007 (SCIDRL) See page 370. Reset: 0x00cc_0008 SCI Pullup and Reduced Read: 0x00cd_0008 Drive Register (SCIPURD) See page 371. ...
Page 84
... Freescale Semiconductor, Inc. System Memory Map Address Register Name Timer 1 (TIM1) and Timer 2 (TIM2) Note: Addresses for TIM1 are at 0x00ce_#### and addresses for TIM2 are at 0x00cf_####. 0x00ce_0000 Timer Input Capture/ 0x00cf_0000 Output Compare Select Register (TIMIOS) See page 324. 0x00ce_0001 Timer Compare Force ...
Page 85
... Freescale Semiconductor, Inc. Address Register Name 0x00ce_0007 Reserved 0x00cf_0007 0x00ce_0008 Timer Toggle on Overflow Read: 0x00cf_0008 Register (TIMTOV) See page 330. Reset: 0x00ce_0009 Timer Control Read: 0x00cf_0009 Register 1 (TIMCTL1) See page 331. Reset: 0x00ce_000a Reserved 0x00cf_000a 0x00ce_000b Timer Control Read: 0x00cf_000b Register 2 (TIMCTL2) See page 332 ...
Page 86
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00ce_000f Timer Flag Register 2 0x00cf_000f (TIMFLG2) See page 337. 0x00ce_0010 Timer Channel 0 Register 0x00cf_0010 High (TIMC0H) See page 338. 0x00ce_0011 Timer Channel 0 Register 0x00cf_0011 Low (TIMC0L) See page 338. 0x00ce_0012 Timer Channel 1 Register ...
Page 87
... Freescale Semiconductor, Inc. Address Register Name 0x00ce_0017 Timer Channel 3 Register Read: 0x00cf_0017 Low (TIMC3L) See page 338. Reset: 0x00ce_0018 Pulse Accumulator Read: 0x00cf_0018 Control Register (TIMPACTL) See page 339. Reset: 0x00ce_0019 Pulse Accumulator Flag Read: 0x00cf_0019 Register (TIMPAFLG) See page 341. ...
Page 88
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00ce_001f Timer Test Register 0x00cf_001f (TIMTST) See page 345. 0x00ce_0020 Unimplemented 0x00ce_ffff 0x00cf_0030 0x00cf_ffff Second Generation FLASH for M•CORE (SGFM) 0x00d0_0000 SGFM Module 0x00d0_0001 Configuration Register (SGFMMCR) See page 213. 0x00d0_0002 SGFM Clock Divider Register (SGFMCLKD) See page 215 ...
Page 89
... Freescale Semiconductor, Inc. Address Register Name 0x00d0_0004 SGFM Test Register Read: (SGFMTST) See page 216. Reset: 0x00d0_0005 Unimplemented 0x00d0_0007 0x00d0_0008 SGFM Security Register Read: 0x00d0_0009 (SGFMSEC) 0x00d0_000a See page 217. 0x00d0_000b Reset: Read: Reset: Read: Reset: Read: Reset Current pin state U = Unaffected Figure 2-4 ...
Page 90
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00d0_000c SGFM Monitor Data 0x00d0_000d Register (SGFMMNTR) 0x00d0_000e See page 219. 0x00d0_000f 0x00d0_0010 SGFM Protection Register 0x00d0_0011 (SGFMPROT) See page 220. 0x00d0_0012 Unimplemented 0x00d0_0013 P = Current pin state U = Unaffected Figure 2-4. Register Summary (Sheet 34 of 37) ...
Page 91
... Freescale Semiconductor, Inc. Address Register Name 0x00d0_0014 SGFM Supervisor Access Read: 0x00d0_0015 Register (SGFMASACC) See page 221. Reset: Read: Reset: 0x00d0_0016 SGFM Data Access Read: 0x00d0_0017 Register (SGFMDACC) See page 223. Reset: Read: Reset: 0x00d0_0018 SGFM Test Status Read: Register (SGFMTSTAT) See page 224 ...
Page 92
... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00d0_001d Unimplemented 0x00d0_001f 0x00d0_0020 SGFM Command Buffer and Register (SGFMCMD) See page 226. 0x00d0_0021 Unimplemented 0x00d0_0023 0x00d0_0024 SGFM Control Register 0x00d0_0025 (SGFMCTL) See page 227. 0x00d0_0026 SGFM Address Register 0x00d0_0027 (SGFMADR) See page 228. ...
Page 93
... Freescale Semiconductor, Inc. Address Register Name 0x00d0_0028 SGFM Data Register Read: RSVD31 0x00d0_0029 (SGFMDATA) 0x00d0_002a See page 229. 0x00d0_002b Reset: Read: RSVD23 Reset: Read: RSVD15 Reset: Read: Reset Current pin state U = Unaffected Figure 2-4. Register Summary (Sheet 37 of 37) MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
Page 94
... Freescale Semiconductor, Inc. System Memory Map Advance Information 94 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 System Memory Map For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
Page 95
... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 3.1 Contents 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.5.1 3.5.1.1 3.5.1.2 3.5.2 3.5.2.1 3.5.2.2 3.5.2.3 3.5.2.4 3.5.3 3.5.3.1 3.5.3.2 3.5.3.3 3.5.3.4 3.5.3.5 3.5.3.6 3.5.3.7 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
Page 96
... Freescale Semiconductor, Inc. Signal Description 3.5.3.8 3.5.3.9 3.5.3.10 3.5.3.11 3.5.4 3.5.4.1 3.5.4.2 3.5.4.3 3.5.5 3.5.5.1 3.5.5.2 3.5.5.3 3.5.5.4 3.5.6 3.5.6.1 3.5.6.2 3.5.7 3.5.8 3.5.8.1 3.5.8.2 3.5.8.3 3.5.8.4 3.5.9 3.5.9.1 3.5.9.2 3.5.9.3 3.5.9.4 3.5.9.5 3.5.9.6 3.5.10 3.5.11 3.5.11.1 3.5.11.2 3.5.11.3 Advance Information 96 Address Bus (A[22:0]) ...
Page 97
... Freescale Semiconductor, Inc. 3.2 Introduction The MMC2114, MMC2113, and MMC2112 are available in three packages: • • • The optional group of pins includes: • • • • • • • • NOTE: The optional pins are either all present or none of them are present. ...
Page 98
... Freescale Semiconductor, Inc. Signal Description 3.3 Package Pinout Summary Refer to: • • • Table 3-1. Package Pinouts (Sheet 144-Pin Package 100-Pin Package — — 9 — — — 14 — — Advance Information 98 Table 3-1 for a summary of the pinouts for the 144-pin and 100- pin LQFP packages ...
Page 99
... Freescale Semiconductor, Inc. Table 3-1. Package Pinouts (Sheet 144-Pin Package 100-Pin Package 24 — — — 29 — — 45 — — — 50 — MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, Pin Number 196-Ball MAPBGA — — ...
Page 100
... Freescale Semiconductor, Inc. Signal Description Table 3-1. Package Pinouts (Sheet 144-Pin Package 100-Pin Package — 60 — — — 65 — — — — 81 — — — 86 — Advance Information 100 Pin Number 196-Ball MAPBGA M10 N10 P10 — — M11 N11 P11 ...
Page 101
... Freescale Semiconductor, Inc. Table 3-1. Package Pinouts (Sheet 144-Pin Package 100-Pin Package — 96 — — 100 — 101 — 102 69 103 70 104 71 105 72 106 73 107 74 108 75 109 76 110 77 111 78 112 79 113 80 114 81 115 82 116 — 117 — 118 83 119 — 120 ...
Page 102
... Freescale Semiconductor, Inc. Signal Description Table 3-1. Package Pinouts (Sheet 144-Pin Package 100-Pin Package 123 85 124 86 125 87 126 88 127 89 128 90 129 91 130 92 131 — 132 — 133 93 134 — 135 94 136 — 137 — 138 95 139 — 140 96 141 97 142 98 143 ...
Page 103
... Freescale Semiconductor, Inc. MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, Signal Description Go to: www.freescale.com Signal Description Package Pinout Summary Advance Information 103 ...
Page 104
... Freescale Semiconductor, Inc. Signal Description 1 D30 2 D29 3 D28 4 D27 5 D26 6 A11 7 D25 D24 11 A10 12 D23 D22 16 D21 17 D20 D19 21 D18 22 D17 D16 D15 D14 31 D13 D12 35 D11 36 D10 Figure 3-2. 144-Pin LQFP Assignments Advance Information 104 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
Page 105
... Freescale Semiconductor, Inc. PA6 1 PA5 2 PA4 3 PA3 4 PA2 5 PA1 6 PA0 7 PB7 8 PB6 9 PB5 10 PB4 PB3 14 PB2 15 PB1 16 PB0 17 PC7 18 PC6 19 PC5 PC4 23 PC3 24 PC2 25 Figure 3-3. 100-Pin LQFP Assignments MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 MOTOROLA For More Information On This Product, Signal Description Go to: www ...
Page 106
... Freescale Semiconductor, Inc. Signal Description Table 3-2. Signal Descriptions (Sheet (1) Alternate Name RESET — RSTOUT SHOWINT EXTAL — XTAL — CLKOUT — PLLEN — PA[7:0], PB[7:0] D[31:0] PC[7:0], PD[7:0] SHS RCON / PE7 TA PE6 TEA PE5 CSE[1:0] PE[4:3] TC[2:0] PE[2:0] R/W PF7 ...
Page 107
... Freescale Semiconductor, Inc. Table 3-2. Signal Descriptions (Sheet (1) Alternate Name MOSI GPIO MISO GPIO SCK GPIO SS GPIO Serial Communication Interface (SCI1 and SCI2) TXD1 GPIO RXD1 GPIO TXD2 GPIO RXD2 GPIO ICOC13 PAI / GPIO ICOC1[2: GPIO ICOC23 PAI / GPIO ICOC2[2: GPIO Queued Analog-to-Digital Converter (QADC) PQA4– ...
Page 108
... Freescale Semiconductor, Inc. Signal Description Table 3-2. Signal Descriptions (Sheet (1) Alternate Name TRST — TCLK — TMS — TDI — TDO — DE — TEST — — V DDF — V SSF V — STBY V — — — — SS Total Total with optional pins 1. Shaded signals are for optional bond-out for 144-pin package. ...
Page 109
... Freescale Semiconductor, Inc. 3.4 Chip Specific Implementation Signal Issues Most modules are designed to allow expanded capabilities if all the module signals to the pads are implemented. This subsection discusses how these modules are implemented on the MMC2114, MMC2113, and MMC2112. 3.4.1 RSTOUT Signal Functions The RSTOUT signal has these multiple functions: • ...
Page 110
... Freescale Semiconductor, Inc. Signal Description 3.4.2 INT Signal Functions The INT signals have these multiple functions: • • NOTE: If the SZEN or PSTEN bits are set during emulation mode, then the corresponding edge port INT functions are lost and will not be emulated externally ...
Page 111
... Freescale Semiconductor, Inc. GPIO [7:4] of SPI module not implemented. • • • The default reset values for the PUPSP bit in SPIPURD is 0. Thus, the pullup function is disabled by default. 3.4.4 Serial Communications Interface (SCI1 and SCI2) Pin Functions Full SCI interface capabilities and GPIO functions using the TXD1/2 and RXD1/2 pins are supported. • ...
Page 112
... Freescale Semiconductor, Inc. Signal Description 3.4.5 Timer 1 and Timer 2 Pin Functions The timer modules can support up to four external pins each. NOTE: Only the pins associated with each timer are controlled by the register bits for the corresponding timer. Full timer port pin functions are supported. ...
Page 113
... Freescale Semiconductor, Inc. 3.5 Signal Descriptions This subsection provides a brief description of the signals. For more detailed information, reference the specific module section. 3.5.1 Reset Signals These signals are used to either reset the chip reset indication. 3.5.1.1 Reset In (RESET) This active-low input signal is used as the external reset request. Reset places the CPU in supervisor mode with default settings for all register bits ...
Page 114
... Freescale Semiconductor, Inc. Signal Description 3.5.2.2 Crystal (XTAL) This output signal is used as a connection to drive an external crystal when the internal oscillator circuit is used. XTAL should be grounded when using an external clock input on EXTAL. 3.5.2.3 Clock Out (CLKOUT) This output signal reflects the internal system clock. ...
Page 115
... Freescale Semiconductor, Inc. 3.5.3.3 Transfer Acknowledge (TA) This input signal indicates that the external data transfer is complete. During a read cycle, when the processor recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the processor recognizes TA, the bus cycle is terminated. This signal is an input in master and emulation modes ...
Page 116
... Freescale Semiconductor, Inc. Signal Description 3.5.3.9 Enable Byte (EB[3:0]) These output signals indicate which byte of data is valid during external cycles. 3.5.3.10 Chip Select (CS[3:0]) These output signals select external devices for external bus transactions. 3.5.3.11 Output Enable (OE) This output signal indicates when an external device can drive data during external read cycles ...
Page 117
... Freescale Semiconductor, Inc. 3.5.5 Serial Peripheral Interface Module Signals These signals are used by the SPI module and may also be configured to be discrete I/O signals. 3.5.5.1 Master Out/Slave In (MOSI) This signal is the serial data output from the SPI in master mode and the serial data input in slave mode ...
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... Freescale Semiconductor, Inc. Signal Description 3.5.6.2 Transmit Data (TXD1 and TXD2) These signals are used for the SCI transmitter data output and are also available for GPIO when not configured for transmitter operation. 3.5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0]) These signals provide the external interface to the timer functions. They may be configured as general-purpose I/O if the timer output function is not needed ...
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... Freescale Semiconductor, Inc. 3.5.9 Debug and Emulation Support Signals These signals are used as the interface to the on-chip JTAG (Joint Test Action Group) controller and also to interface to the OnCE logic. 3.5.9.1 Test Reset (TRST) This active-low input signal is used to initialize the JTAG and OnCE logic asynchronously ...
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... Freescale Semiconductor, Inc. Signal Description 3.5.10 Test Signal (TEST) This input signal (TEST) is reserved for factory testing only and should be connected to V 3.5.11 Power and Ground Signals These signals provide system power and ground to the chip. Multiple signals are provided for adequate current capability. All power supply signals must have adequate bypass capacitance for high-frequency noise suppression ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 Section 4. Chip Configuration Module (CCM) 4.1 Contents 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.3.1 4.7.3.2 4.7.3.3 4.7.3.4 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4 ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 4.2 Introduction The chip configuration module (CCM) controls the chip configuration and mode of operation. 4.3 Features The CCM performs these operations. • • • • • • 4.4 Modes of Operation The CCM configures the chip for four modes of operation: • ...
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... Freescale Semiconductor, Inc. 4.4.1 Master Mode In master mode, the internal central processor unit (CPU) can access external memories and peripherals. Full master mode functionality requires the bonding out of the optional pins. The external bus consists of a 32-bit data bus and 23 address lines. Available bus control signals include R/W, TC[2:0], TSIZ[1:0], TA, TEA, OE, and EB[3:0] ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 4.5 Block Diagram 4.6 Signal Descriptions Table 4-1 information, refer to RCON PLLEN D[26, 23, 22, 21, 19, 18, 17, 16] Advance Information 124 RESET CONFIGURATION CHIP MODE SELECTION BOOT DEVICE SELECTION CHIP CONFIGURATION REGISTER RESET CONFIGURATION REGISTER CHIP IDENTIFICATION REGISTER CHIP TEST REGISTER Figure 4-1 ...
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... Freescale Semiconductor, Inc. 4.7 Memory Map and Registers This subsection provides a description of the memory map and registers. 4.7.1 Programming Model The CCM programming model consists of these registers: • • • • Some control register bits are implemented as write-once bits. These bits are always readable, but once the bit has been written, additional writes have no effect, except during debug and test operations ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 4.7.2 Memory Map Table 4-3. Chip Configuration Module Memory Map Address Bits 31–16 0x00c1_0000 Chip Configuration Register (CCR) 0x00c1_0004 Reset Configuration Register (RCON) 0x00c1_0008 Chip Test Register (CTR) 0x00c1_000c CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. Writing to reserved addresses has no effect ...
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... Freescale Semiconductor, Inc. LOAD — Pad Driver Load Bit The LOAD bit selects full or default drive strength for selected pad output drivers. For maximum capacitive load, set the LOAD bit to select full drive strength. For reduced power consumption, clear the LOAD bit to select default drive strength. ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) SZEN — TSIZ[1:0] Enable Bits This read/write bit enables the TSIZ[1:0] function of the external pins. PSTEN — PSTAT[3:0] Signal Enable Bits This read/write bit enables the PSTAT[3:0] function of the external pins. SHINT — Show Interrupt Bit The SHINT bit allows visibility to any active interrupt request to the processor ...
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... Freescale Semiconductor, Inc. BMT[1:0] — Bus Monitor Timing Field The BMT field selects the timeout time for the bus monitor as shown in Table Table 4-2 4.7.3.2 Reset Configuration Register The Reset Configuration Register (RCON read-only register; writing to RCON has no effect. At reset, RCON determines the default operation of certain chip functions ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) RPLLSEL — PLL Mode Select Bit When the PLL is enabled, the read-only RPLLSEL bit reflects the default PLL mode. The default PLL mode can be overridden during reset configuration. If the default mode is overridden, the PLLSEL bit in the clock module SYNSR reflects the PLL mode. RPLLREF — ...
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... Freescale Semiconductor, Inc. BOOTSEL — Boot Select Bit This read-only bit reflects the default selection for the boot device. The default function of the boot select can be overridden during reset configuration. If the default mode is overridden, the CSEN bit in CSCR0 bit reflects the boot device configuration. ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) PIN[7:0] — Part Identification Number Field This read-only field contains a unique identification number for the part. PRN[7:0] — Part Revision Number Field This read-only field contains the full-layer mask revision number. This number is increased by one for each new full-layer mask set of this part ...
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... Freescale Semiconductor, Inc. 4.8 Functional Description Six functions are defined within the chip configuration module: 1. Reset configuration 2. Chip mode selection 3. Boot device selection 4. Output pad strength configuration 5. Clock mode selection 6. Module configuration These functions are described here. 4.8.1 Reset Configuration During reset, the pins for the reset override functions are immediately configured to known states ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) If the external RCON pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins. (See the levels on the external configuration pins to allow for module configuration ...
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... Freescale Semiconductor, Inc. 4.8.2 Chip Mode Selection The chip mode is selected during reset and reflected in the MODE field of the Chip Configuration Register (CCR). (See Configuration cannot be changed. configuration. Chip Configuration Master mode Single-chip mode FAST mode Emulation mode 1. Modifying the default configurations is possible only if the external RCON pin is asserted. ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) Chip select disabled (32-bit port size) Chip select enabled with 16-bit port size Chip select enabled with 32-bit port size 1. CSCR1 CSEN is initially set only in emulation mode when booting from internal memory and is cleared otherwise. ...
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... Freescale Semiconductor, Inc. 4.8.4 Output Pad Strength Configuration Output pad strength is determined during reset configuration as shown in Table capability for each setting. Once reset is exited, the output pad strength configuration can be changed by programming the LOAD bit of the Chip Configuration Register. Output pads configured for default strength Output pads configured for full strength 1 ...
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... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 4.8.6 Internal FLASH Configuration The internal FLASH in the MMC2113 and MMC2114 is always enabled. 4.9 Reset Reset initializes CCM registers to a known startup state as described in 4.7 Memory Map and at reset as described in 4.10 Interrupts The CCM does not generate interrupt requests. ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 5.1 Contents 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.6 5.6.1 5.6.2 5.7 5.7.1 5.7.1.1 5.7.1.2 5.7.1.3 5.7.1.4 5.7.1.5 5.7.1.6 5.7.1.7 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 5.7.3 5.7.3.1 5.7.3.2 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Reset Controller Module 5.2 Overview The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and then to keep a history of what caused the reset. The power management CPU (PMM) control registers that generate low-voltage detect (LVD) bits are implemented in the reset module ...
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... Freescale Semiconductor, Inc. 5.4 Block Diagram Figure 5-1 explained in the following sections. 5.5 Signals Table 5-1 The signals are described in the following paragraphs. RESET pin RSTOUT pin 1. RESET is always synchronized except when in low-power stop mode. MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Reset Controller Module 5.5.1 RESET Asserting the external RESET pin for at least four rising CLKOUT edges causes the external reset request to be recognized and latched. 5.5.2 RSTOUT This active-low output signal is driven low when the internal reset controller module resets the chip. When RSTOUT is active, the user can drive override options on the data bus ...
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... Freescale Semiconductor, Inc. 5.6.1 Reset Control Register The Reset Control Register (RCR) allows software control for requesting a reset, for independently asserting the external RSTOUT pin, and for controlling low-voltage detect (LVD) functions. Address: 0x00c4_0000 Read: SOFTRST Write: Reset: Note: Reset dependent SOFTRST — ...
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... Freescale Semiconductor, Inc. Reset Controller Module LVDF — LVD Flag The LVDF bit indicates the low-voltage detect status if LVDE is set. Write clear the LVDF bit. NOTE: The setting of this flag causes an LVD interrupt if LVDE and LVDIE bits are set and LVDRE is cleared when the supply voltage V ...
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... Freescale Semiconductor, Inc. 5.6.2 Reset Status Register The Reset Status Register (RSR) contains a status bit for every reset source. When reset is entered, the cause of the reset condition is latched along with a value of 0 for the other reset sources that were not pending at the time of the reset condition ...
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... Freescale Semiconductor, Inc. Reset Controller Module POR — Power-On Reset Flag POR indicates that the last reset was caused by a power-on reset. EXT — External Reset Flag EXT indicates that the last reset was caused by an external device asserting the external RESET pin. ...
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... Freescale Semiconductor, Inc. 5.7 Functional Description 5.7.1 Reset Sources Table 5-3 controller. Power on External RESET pin (not stop mode) External RESET pin (during stop mode) Watchdog timer Loss of clock Loss of lock Software LVD reset To protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the end of the current bus cycle ...
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... Freescale Semiconductor, Inc. Reset Controller Module 5.7.1.1 Power-On Reset At power up, the reset controller asserts RSTOUT. RSTOUT continues to be asserted until V if PLL clock mode is selected, until the PLL achieves phase lock. Then after approximately another 512 cycles, RSTOUT is negated and the part begins operation ...
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... Freescale Semiconductor, Inc. 5.7.1.5 Loss of Lock Reset This reset condition occurs in PLL clock mode when the LOLRE bit in the SYNCR register is set and the PLL loses lock. The reset controller asserts RSTOUT for approximately 512 cycles after the PLL has acquired lock. The part then exits reset and resumes operation. ...
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... Freescale Semiconductor, Inc. Reset Controller Module 1 LOSS OF CLOCK LOSS OF LOCK RESET PIN OR WD TIMEOUT OR SW RESET NEGATE RSTOUT Advance Information 150 ENABLE BUS MONITOR Y 6 BUS CYCLE COMPLETE ASSERT RSTOUT AND LATCH RESET STATUS 8 RESET NEGATED PLL MODE WAIT 512 CLKOUT CYCLES ...
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... Freescale Semiconductor, Inc. 5.7.2.1 Synchronous Reset Requests In this discussion, the reference in parentheses refer to the state numbers in If either the external RESET pin is asserted by an external device for at least four rising CLKOUT edges (3), or the watchdog timer times out, or software requests a reset, the reset control logic latches the reset request internally and enables the bus monitor (5) ...
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... Freescale Semiconductor, Inc. Reset Controller Module 5.7.3 Concurrent Resets This section describes the concurrent resets the previous discussion references in parentheses refer to the state numbers in Figure 5.7.3.1 Reset Flow If a power-on reset or low-voltage detect condition is detected during any reset sequence, the reset sequence starts immediately (0). ...
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... Freescale Semiconductor, Inc. If the RSR bits are latched (4) during the internal reset sequence with the RESET pin not asserted and no SOFT or WDR event, then the LOC and/or LOL bits are the only bits set. For a LVD reset, the LVD bit in the Reset Status Register (RSR) is set, ...
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... Freescale Semiconductor, Inc. Reset Controller Module Advance Information 154 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Reset Controller Module For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 6.1 Contents 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.4.9 6.4.10 6.4.11 6.4.12 6.4.13 6.4.14 6.5 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Power Management 6.2 Introduction The following features support low power operation. • • • 6.3 Low-Power Modes The system enters a low-power mode by execution of a STOP, WAIT, or DOZE instruction.This idles the CPU with no cycles active. An internal signal indicates to the system and clock controller to power down and stop the clocks appropriately ...
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... Freescale Semiconductor, Inc. 6.3.2 Wait Mode Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU to exit from wait mode. ...
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... Freescale Semiconductor, Inc. Power Management 6.4 Peripheral Behavior in Low-Power Modes 6.4.1 Reset A power-on reset (POR) will always cause a chip reset and exit from any low-power mode. In wait and doze modes, asserting the external RESET pin for at least four clocks will cause an external reset that will reset the chip and exit any low-power modes ...
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... Freescale Semiconductor, Inc. for the OSC to restart is dependent upon the startup time of the crystal used. Power consumption can be reduced in stop mode by disabling either or both of these functions via the STMPD bits of the Synthesizer Control Register (SYNCR). See Register. The external CLKOUT signal may be enabled during low-power stop (if the PLL is still enabled) to support systems using this signal as the clock source ...
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... Freescale Semiconductor, Inc. Power Management 6.4.4 JTAG The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power mode. Toggling TCLK during any low-power mode will increase the system current consumption ...
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... Freescale Semiconductor, Inc. 6.4.8 FLASH The FLASH low-power state if not being accessed. No recovery time is required after exit from any low-power mode. 6.4.9 Queued Analog-to-Digital Converter (QADC) Setting the queued analog-to-digital converter (QADC) STOP bit (QSTOP) will disable the QADC. The QADC is unaffected by either wait or doze mode and may generate an interrupt to exit these modes ...
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... Freescale Semiconductor, Inc. Power Management 6.4.11 Programmable Interrupt Timers (PIT1 and PIT2) In stop mode (or in doze mode programmed), the programmable interrupt timer (PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the stopped value ...
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... Freescale Semiconductor, Inc. In stop mode (or doze mode programmed), the SCIs stop immediately and freeze their operation, register values, state machines, and external pins. During these modes, the SCI clocks are shut down. Coming out of the doze or stop modes, returns the SCIs to operation from the state prior to the low-power mode entry ...
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... Freescale Semiconductor, Inc. Power Management Table 6-1. CPU and Peripherals in Low-Power Modes Module Run Mode CPU Enabled Reset Enabled Clock Enabled OnCE Enabled JTAG Enabled Interrupt controller Enabled Edge port Enabled RAM Enabled FLASH Enabled QADC Enabled Watchdog timer Enabled PIT1 and PIT2 ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 Section 7. M•CORE M210 Central Processor Unit (CPU) 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.2 Introduction The M•CORE M210 central processor unit (CPU) architecture is one of the most compact, full 32-bit core implementations available. The ...
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... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) A strictly defined load/store architecture minimizes control complexity. Use of a fixed, 16-bit instruction encoding significantly lowers the memory bandwidth needed to sustain a high rate of instruction execution, and careful selection of the instruction set allows the code density and overall memory efficiency of the CPU architecture to surpass those of complex instruction set computer (CISC) architectures ...
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... Freescale Semiconductor, Inc. 7.4 Microarchitecture Summary Figure 7-1 The processor utilizes a 4-stage pipeline for instruction execution. The instruction fetch, instruction decode/register file read, execute, and register file writeback stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. ...
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... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) Arithmetic and logical operations are executed in a single cycle. Multiplication is implemented with a 2-bit per clock, overlapped-scan, modified Booth algorithm with early-out capability, to reduce execution time for operations with small multipliers. Divide is implemented with a 1-bit per clock early-in algorithm ...
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... Freescale Semiconductor, Inc. 7.5 Programming Model Figure 7-2 model is defined differently for supervisor and user privilege modes. By convention, in both modes R15 serves as the link register for subroutine calls typically used as the stack pointer. USER PROGRAMMER’S * BIT 0 OF PSR The user programming model consists of 16 general-purpose 32-bit registers (R0– ...
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... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) The supervisor programming model consists of the user model plus 16 additional 32-bit general-purpose registers (R0–R15), called the alternate file and a set of status/control registers (CR0–CR12) which includes the entire PSR. Setting the S bit in the PSR enables supervisor mode operation ...
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... Freescale Semiconductor, Inc. 7.6 Data Format Summary The operand data formats supported by the integer unit are standard two’s-complement data formats. The operand size for each instruction is either explicitly encoded in the instruction (load/store instructions) or implicitly defined by the instruction operation (index operations, byte extraction) ...
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... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) 7.7 Operand Addressing Capabilities The M•CORE processor accesses all memory operands through load and store instructions, transferring data between the general-purpose registers and memory. Register-plus-four-bit scaled displacement addressing mode is used for load and store instructions addressing byte, half-word, and word data ...
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... Freescale Semiconductor, Inc. Table 7-1. M•CORE Instruction Set (Sheet Mnemonic ABS Absolute Value ADDC Add with C Bit ADDI Add Immediate ADDU Add Unsigned AND Logical AND ANDI Logical AND Immediate ANDN AND NOT ASR Arithmetic Shift Right ASRC Arithmetic Shift Right, Update C Bit ...
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... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) Table 7-1. M•CORE Instruction Set (Sheet Mnemonic JMP Jump JMPI Jump Indirect JSR Jump to Subroutine JSRI Jump to Subroutine Indirect LD.[BHW] Load LDM Load Multiple Registers LDQ Load Register Quadrant LOOPT Decrement with C-Bit Update and Branch if Condition True ...
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... Freescale Semiconductor, Inc. Table 7-1. M•CORE Instruction Set (Sheet Mnemonic XOR Exclusive OR XSR Extended Shift Right XTRB0 Extract Byte 0 XTRB1 Extract Byte 1 XTRB2 Extract Byte 2 XTRB3 Extract Byte 3 ZEXTB Zero-Extend Byte ZEXTH Zero-Extend Half-Word 1. 1 cycle if branch not taken, 2 cycles if branch taken 2 ...
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... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) Advance Information 176 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 M•CORE M210 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 8.1 Contents 8.2 8.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.7.2.1 8.7.2.2 8.7.2.3 8.7.2.4 8.7.2.5 8.7.2.6 8.7.2.7 8.7.2.8 8.7.2.9 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.4.1 8.8.4.2 8.8.4.3 8.8.5 MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module 8.2 Introduction The interrupt controller collects requests from multiple interrupt sources and provides an interface to the CPU interrupt logic. 8.3 Features Features of the interrupt controller module include: • • • • • • • • • ...
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... Freescale Semiconductor, Inc. 8.5 Block Diagram INTERRUPT SOURCES PRIORITY OR LEVEL 40 SELECT BITS PLSR PLSR PLSR PLSR Figure 8-1. Interrupt Controller Block Diagram 8.6 External Signals No interrupt controller signals connect off-chip. 8.7 Memory Map and Registers This subsection describes the memory map (see registers. MMC2114 • ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module 8.7.1 Memory Map Table 8-1. Interrupt Controller Module Memory Map Address Bits 31–24 0x00c5_0000 Interrupt Control Register (ICR) 0x00c5_0004 0x00c5_0008 0x00c5_000c 0x00c5_0010 0x00c5_0014 0x00c5_0018 0x00c5_001c 0x00c5_0020 through 0x00c5_003c Priority Level Select Registers (PLSR0–PLSR39) 0x00c5_0040 ...
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... Freescale Semiconductor, Inc. 8.7.2 Registers This subsection contains a description of the interrupt controller module register set. 8.7.2.1 Interrupt Control Register The 16-bit Interrupt Control Register (ICR) selects whether interrupt requests are autovectored or vectored, and if vectored, whether fast interrupts generate a different vector number than normal interrupts. ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module ME — Mask Enable Bit The read/write ME bit enables interrupt masking. Reset clears ME. MFI — Mask Fast Interrupts Bit The read/write MFI bit enables masking of fast interrupt requests. Reset clears MFI. MASK[4:0] — Interrupt Mask Field The read/write MASK[4:0] field determines which interrupt priority levels are masked ...
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... Freescale Semiconductor, Inc. 8.7.2.2 Interrupt Status Register The 16-bit, read-only Interrupt Status Register (ISR) reflects the state of the interrupt controller outputs to the CPU. Writes to this register have no effect and are terminated normally. Address: 0x00c5_0002 and 0x00c5_0003 Read: Write: Reset: Read: Write: Reset: INT — ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module 8.7.2.3 Interrupt Force Registers The two 32-bit read/write Interrupt Force Registers (IFRH and IFRL) individually force interrupt source requests. Address: 0x00c5_0004 through 0x00c5_0007 Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: ...
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... Freescale Semiconductor, Inc. Address: 0x00c5_0008 through 0x00c5_000b Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: IF[39:0] — Interrupt Force Field This read/write field forces interrupt requests at the corresponding source numbers. Reference to determine which bit(s) to set in this register. IFRH and IFRL allow software generation of interrupt requests for functional or debug purposes ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module 8.7.2.4 Interrupt Pending Register The 32-bit, read-only Interrupt Pending Register (IPR) reflects any currently pending interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated normally. Address: 0x00c5_000c through 0x00c5_000f ...
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... Freescale Semiconductor, Inc. 8.7.2.5 Normal Interrupt Enable Register The read/write, 32-bit Normal Interrupt Enable Register (NIER) individually enables any current pending interrupts which are assigned to each priority level as a normal interrupt source. Enabling an interrupt source which has an asserted request causes that request to become pending, and a request to the CPU is asserted if not already outstanding ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module 8.7.2.6 Normal Interrupt Pending Register The read-only, 32-bit Normal Interrupt Pending Register (NIPR) reflects any currently pending normal interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated normally. Address: 0x00c5_0014 through 0x00c5_0017 ...
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... Freescale Semiconductor, Inc. 8.7.2.7 Fast Interrupt Enable Register The read/write, 32-bit Fast Interrupt Enable Register (FIER) enables any current pending interrupts which are assigned at each priority level as a fast interrupt source. Enabling an interrupt source which has an asserted request causes that interrupt to become pending, and a request to the CPU is asserted if not already outstanding ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module 8.7.2.8 Fast Interrupt Pending Register The read-only, 32-bit Fast Interrupt Pending Register (FIPR) reflects any currently pending fast interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated normally. Address: 0x00c5_001c through 0x00c5_001f ...
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... Freescale Semiconductor, Inc. 8.7.2.9 Priority Level Select Registers The read/write 8-bit Priority Level Select Registers (PLSRx) are 40 read/write, 8-bit priority level select registers PLSR0–PLSR39, one for each of the interrupt source. The PLSRx register assigns a priority level to interrupt source x. Address: 0x00c5_0040 through 0x00c5_0067 ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module 8.8.1 Interrupt Sources and Prioritization Each interrupt source in the system sends a unique signal to the interrupt controller interrupt sources are supported. Each interrupt source can be programmed to one of 32 priority levels by programing the PLS bits of the PLSR in the interrupt controller. The highest priority level is 31 and lowest priority level is 0 ...
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... Freescale Semiconductor, Inc interrupt is pending at a given priority level and both the corresponding FIER and NIER bits are set, then both the corresponding FIPR and NIPR bits are set, assuming these bits are not masked. Fast interrupt requests always have priority over normal interrupt requests, even if the normal interrupt request higher priority level than the highest fast interrupt request ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module level, then the interrupt service routine to determine the correct source of the interrupt. If the AE bit is 0, then each interrupt request is presented with a vector number. The low five bits of the vector number (4–0) are determined based on the highest pending priority, with active fast interrupts having priority over active normal interrupts ...
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... Freescale Semiconductor, Inc. 8.8.4 Interrupt Configuration After reset, all interrupts are disabled by default. To properly configure the system to handle interrupt requests, configuration must be performed at three levels: • • • Configure the CPU first, the interrupt controller second, and the local interrupt sources last. ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module determine if the fast interrupt vector number separate from the normal interrupt vector. 8.8.4.3 Interrupt Source Configuration Each module that is capable of generating an interrupt request has an interrupt request enable/disable bit. To allow the interrupt source to be asserted, set the local interrupt enable bit. ...
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... Freescale Semiconductor, Inc. Table 8-6. Interrupt Source Assignment Source Module Flag 0 PF1 Queue 1 conversion pause 1 CF1 Queue 1 conversion complete Write CF1 = 0 after reading CF1 = 1 ADC 2 PF2 Queue 2 conversion pause 3 CF2 Queue 2 conversion complete Write CF2 = 0 after reading CF2 = 1 4 MODF Mode fault ...
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... Freescale Semiconductor, Inc. Interrupt Controller Module Table 8-6. Interrupt Source Assignment (Continued) Source Module Flag 23 C0F Timer channel 0 24 C1F Timer channel 1 25 C2F Timer channel 2 26 TIM2 C3F Timer channel 3 27 TOF Timer overflow 28 PAIF Pulse accumulator input 29 PAOVF Pulse accumulator overflow ...
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... Freescale Semiconductor, Inc. Advance Information — MMC2114, MMC2113, and MMC2112 Section 9. Static Random Access Memory (SRAM) 9.1 Contents 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.2 Introduction Features of the static random access memory (SRAM) include: • • • • • • ...
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... Freescale Semiconductor, Inc. Static Random Access Memory (SRAM) 9.3 Modes of Operation Access to the SRAM is not restricted in any way. The array can be accessed in supervisor and user modes. NOTE: The MMC2113 may contain more than 8K of internal SRAM, but only the 8K range from 0x0080_0000 to 0x0080_1fff is tested and guaranteed to be operational ...