MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 565

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
As an input, this signal provides multiple functions such as:
If used to enter debug mode, DE must be negated before the processor
exits debug mode to prevent a still low signal from being unintentionally
recognized as another debug request. Also, asserting this signal to enter
debug mode may prevent external logic from seeing the processor
output acknowledgment since the external pullup may not be able to pull
the signal negated before the handshake is asserted. Finally, if using this
signal to enable OnCE outside of reset it may be seen as a request to
enter debug mode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
The main function is a means of entering debug mode from an
external command controller. This signal, when asserted, causes
the CPU to finish the current instruction being executed, save the
instruction pipeline information, enter debug mode, and wait for
commands to be entered from the serial debug input line. This
input must be asserted for at least three system clocks, sampled
with the rising CLKOUT edge. This function is ignored during
reset. While the processor is in debug mode, this signal is still
sampled but has no effect until debug mode is exited.
Another input function is to enable OnCE. This is an alternate
method to the ENABLE_MCU_ONCE JTAG command to enable
the OnCE logic to be accessible via the JTAG interface. This input
signal must be asserted low (while in the test-logic-reset state with
POR/TRST not asserted) for at least two TCLK rising edges. Once
enabled, the OnCE will remain enabled until the next POR or
TRST resets.
Another input function is as a wake-up event from a low-power
mode of operation. Asynchronously asserting this signal will cause
the clock controller to restart. This signal must be held asserted
until the M•CORE receives three valid rising edges on the system
clock. Then the processor will exit the low-power mode and go into
debug mode.
JTAG Test Access Port and OnCE
Go to: www.freescale.com
JTAG Test Access Port and OnCE
Top-Level Test Access Port (TAP)
Advance Information
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