MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 25

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
20.7
20.7.1
20.7.1.1
20.7.1.2
20.7.1.3
20.7.2
20.7.2.1
20.7.2.2
20.7.2.3
20.8
20.8.1
20.8.2
20.9
20.9.1
20.9.2
20.9.3
20.9.4
20.9.5
20.10 Bus Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
20.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
21.1
21.2
21.3
21.4
21.5
21.6
21.6.1
21.6.2
21.7
21.8
Freescale Semiconductor, Inc.
For More Information On This Product,
Bus Master Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Bus Exception Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Transfer Error Termination . . . . . . . . . . . . . . . . . . . . . . . . . 540
Transfer Abort Termination . . . . . . . . . . . . . . . . . . . . . . . . 540
Emulation Chip-Selects (CSE[1:0]) . . . . . . . . . . . . . . . . . .540
Internal Data Transfer Display (Show Cycles) . . . . . . . . . . 541
Show Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Transfer Code (TC[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Processor Status (PSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . 543
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Optional Wait States (X2W) . . . . . . . . . . . . . . . . . . . . . . 536
State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Optional Wait States (X2W) . . . . . . . . . . . . . . . . . . . . . . 538
State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
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Section 21. Chip Select Module
Table of Contents
Advance Information
Table of Contents
25