MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 605

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.14.12.4 Writeback Bus Register
22.14.12.5 Processor Status Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
TC — Prefetch Transfer Code
The Writeback Bus Register (WBBR) is a means of passing operand
information between the CPU and the external command controller.
Whenever the external command controller needs to read the contents
of a register or memory location, it forces the device to execute an
instruction that brings that information to WBBR.
For example, to read the content of processor register r0, a MOV r0,r0
instruction is executed, and the result value of the instruction is latched
into the WBBR. The contents of WBBR can then be delivered serially to
the external command controller.
To update a processor resource, this register is initialized with a data
value to be written, and a MOV instruction is executed which uses this
value as a write-back data value. The FFY bit in the CTL Register forces
the value of the WBBR to be substituted for the normal source value of
a MOV instruction, thus allowing updates to processor registers to be
performed.
The Processor Status Register (PSR) is a 32-bit latch used to read or
write the M•CORE Processor Status Register. Whenever the external
command controller needs to save or modify the contents of the
M•CORE Processor Status Register, the PSR is used. This register is
affected by the operations performed in debug mode and must be
restored by the external command controller when returning to normal
mode.
This control field is used to drive the CPU TC2–TC0 outputs on the
first instruction pre-fetch caused by issuing a OnCE command with
the GO bit set and not ignored. It should typically be set to indicate a
supervisor instruction access, for example, 0b110. This field should
be restored to its original value after a debug session is completed,
for example, when a OnCE command is issued with the GO and EX
bits set and not ignored.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
JTAG Test Access Port and OnCE
Functional Description
Advance Information
605