MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 415

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.8.2 Slave Mode
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
Clearing the MSTR bit in SPICR1 puts the SPI in slave mode. The SCK
pin is the SPI clock input from the master, and the SS pin is the
slave-select input. For a transmission to occur, the SS pin must be driven
low and remain low until the transmission is complete.
The MSTR bit and the SPC0 bit in SPICR2 control the function of the
data pins, MOSI and MISO. The SS input also controls the MISO pin. If
SS is low, the MSB in the shift register shifts out on the MISO pin. If SS
is high, the MISO pin is in a high impedance state, and the slave ignores
the SCK input.
When using peripherals with full-duplex capability, do not simultaneously
enable two receivers that drive the same MISO output line.
As long as only one slave drives the master input line, it is possible for
several slaves to receive the same transmission simultaneously.
If the CPHA bit in SPICR1 is clear, odd-numbered edges on the SCK
input latch the data on the MOSI pin. Even-numbered edges shift the
data into the LSB position of the SPI shift register and shift the MSB out
to the MISO pin.
If the CPHA bit is set, even-numbered edges on the SCK input latch the
data on the MOSI pin. Odd-numbered edges shift the data into the LSB
position of the SPI shift register and shift the MSB out to the MISO pin.
The transmission is complete after the eighth shift. The received data
transfers to SPIDR, setting the SPIF flag in SPISR.
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface Module (SPI)
Go to: www.freescale.com
Serial Peripheral Interface Module (SPI)
Functional Description
Advance Information
415