MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 600

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
22.14.8.2 Trace Operation
22.14.9 Methods of Entering Debug Mode
22.14.9.1 Debug Request During RESET
Advance Information
600
To initiate trace mode operation:
When debug mode is exited, the counter is decremented after each
execution of an instruction. Interrupts can be serviced, and all
instructions executed (including interrupt services) will decrement the
trace counter.
When the trace counter decrements to zero, the OnCE control logic
requests that the processor re-enter debug mode, and the trace
occurrence bit TO in the OSR is set to indicate that debug mode has
been requested as a result of the trace count function. The trace counter
allows a minimum of two instructions to be specified for execution prior
to entering trace (specified by a count value of one), unless sequential
breakpoint control operation is enabled in the OCR. In this case, a value
of zero (indicating a single instruction) is allowed.
The PM status field in the OSR indicates that the CPU has entered
debug mode. The following paragraphs discuss conditions that invoke
debug mode.
When the DR bit in the OCR is set, assertion of RESET causes the
device to enter debug mode. In this case the device may fetch the reset
1. Load the OTC Register with a value. This value must be non-zero,
2. Initialize the program counter and Instruction Register in the
3. Set the TME bit in the OCR.
4. Release the processor from debug mode by executing the
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unless sequential breakpoint control operation is enabled in the
OCR Register. In this case, a value of zero (indicating a single
instruction) is allowed.
CPUSCR with values corresponding to the start location of the
instruction(s) to be executed real-time.
appropriate command issued by the external command controller.
JTAG Test Access Port and OnCE
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