MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 569

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.5.3 SAMPLE/PRELOAD Instruction
22.5.4 ENABLE_MCU_ONCE Instruction
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
always a logic 1. The remaining 31 bits are also set to fixed values on
the rising edge of TCLK following entry into the capture-DR state.
IDCODE is the default instruction placed into the Instruction Shift
Register when the top-level TAP resets. Thus, after a TAP reset, the
IDCODE (data) register will be selected automatically.
The SAMPLE/PRELOAD instruction provides two separate functions.
First, it obtains a sample of the system data and control signals present
at the input pins and just prior to the boundary scan cell at the output
pins. This sampling occurs on the rising edge of TCLK in the capture-DR
state when an instruction encoding of hex 2 is resident in the Instruction
Shift Register. The user can observe this sampled data by shifting it
through the Boundary Scan Register to the output TDO by using the
shift-DR state. Both the data capture and the shift operation are
transparent to system operation.
The user is responsible for providing some form of external
synchronization to achieve meaningful results because there is no
internal synchronization between TCLK and the system clock.
The second function of the SAMPLE/PRELOAD instruction is to initialize
the Boundary Scan Register update cells before selecting EXTEST or
CLAMP. This is achieved by ignoring the data being shifted out of the
TDO pin while shifting in initialization data. The update-DR state in
conjunction with the falling edge of TCLK can then transfer this data to
the update cells. This data will be applied to the external output pins
when EXTEST or CLAMP instruction is applied.
The ENABLE_MCU_ONCE is a public instruction to enable the
M•CORE OnCE TAP controller. When the OnCE TAP controller is
enabled, the top-level TAP controller connects the internal OnCE TDO
to the pin TDO and remains in the run-test/idle state. It will remain in this
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
Junction Temperature Determination
JTAG Test Access Port and OnCE
Advance Information
569