MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 343

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MMC2114CFCAG33

Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheets

Specifications of MMC2114CFCAG33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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16.7.18 Timer Port Data Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: TIM1 — 0x00ce_001d
Reset:
Read: Anytime; read pin state when corresponding TIMDDR bit is 0;
read pin driver state when corresponding TIMDDR bit is 1
Write: Anytime
PORTT[3:0] — Timer Port Input Capture/Output Compare Data Bits
Read:
Write:
Data written to TIMPORT is buffered and drives the pins only when
they are configured as general-purpose outputs.
Reading an input (DDR bit = 0) reads the pin state; reading an output
(DDR bit = 1) reads the latch.
Writing to a pin configured as a timer output does not change the pin
state.
Freescale Semiconductor, Inc.
For More Information On This Product,
TIM2 — 0x00cf_001d
Figure 16-23. Timer Port Data Register (TIMPORT)
Bit 7
0
0
Timer Modules (TIM1 and TIM2)
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
6
0
0
5
0
0
4
0
0
PORTT3
3
0
Timer Modules (TIM1 and TIM2)
PORTT2
Memory Map and Registers
2
0
Advance Information
PORTT1
1
0
PORTT0
Bit 0
0
343

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