MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 497

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.10.6.3 Externally Gated Single-Scan Mode
19.10.6.4 Interval Timer Single-Scan Mode
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The QADC provides external gating for queue 1 only. When externally
gated single-scan mode is selected, the input level on the associated
external trigger pin enables and disables queue execution. The polarity
of the external gate signal is fixed so that only a high level opens the gate
and a low level closes the gate. Once the gate is open, each CCW is
read and the indicated conversions are performed until the gate is
closed. Queue scan must be enabled by setting the single-scan enable
bit for queue 1. If a pause is encountered, the pause flag does not set,
and execution continues without pausing.
While the gate is open, queue 1 executes one time. Each CCW is read
and the indicated conversions are performed until an end-of-queue
condition is encountered. When queue 1 completes, the QADC sets the
completion flag (CF1) and clears the single-scan enable bit. Set the
single-scan enable bit again to allow another scan of queue 1 to be
initiated during the next open gate.
If the gate closes before queue 1 completes execution, the current CCW
completes, execution of queue 1 stops, the single-scan enable bit is
cleared, and the PF1 bit is set. The CWPQ1 field can be read to
determine the last valid conversion in the queue. The single-scan enable
bit must be set again and the PF1 bit should be cleared before another
scan of queue 1 is initiated during the next open gate. The start of
queue 1 is always the first CCW in the CCW table.
Because the gate level is only sampled after each conversion during
queue execution, closing the gate for a period less than a conversion
time interval does not guarantee the closure will be captured.
Both queues can use the periodic/interval timer in a single-scan queue
operating mode. The timer interval can range from 2
cycles in binary multiples. When the interval timer single-scan mode is
selected and the single-scan enable bit is set in QACR1 or QACR2, the
timer begins counting. When the time interval elapses, an internal trigger
event is generated to start the queue and the QADC begins execution
with the first CCW.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
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Advance Information
17
Digital Control
QCLK
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