MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 553

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: 0x00c2_00006 and 0x00c2_0007
Reset:
Reset:
Read:
Read:
Write:
Write:
SO — Supervisor-Only Bit
RO — Read-Only Bit
The SO bit restricts user mode access to the address range defined
by the corresponding chip select. If the SO bit is 1, only supervisor
mode access is permitted. If the SO bit is 0, both supervisor and user
level accesses are permitted.
When an access is made to a memory space assigned to the chip
select, the chip select logic compares the SO bit with bit 2 of the
internal transfer code, which indicates whether the access is at the
supervisor or user level. If the chip select logic detects a protection
violation, the access is ignored.
The RO bit restricts write accesses to the address range defined by
the corresponding chip select. If the RO bit is 1, only read access is
permitted. If the RO bit is 0, both read and write accesses are
permitted.
When an access is made to a memory space assigned to the chip
select, the chip select logic compares the RO bit with the internal
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Only supervisor mode accesses allowed; user mode accesses
0 = Supervisor and user mode accesses allowed
Figure 21-5. Chip Select Control Register 3 (CSCR3)
Bit 15
Bit 7
SO
0
0
0
ignored by chip select logic
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= Writes have no effect and the access terminates without a transfer error exception.
RO
Chip Select Module
14
0
6
0
0
PS
13
1
5
0
0
WWS
12
1
4
0
0
WE
11
1
3
0
0
Memory Map and Registers
WS2
10
1
2
0
0
Advance Information
Chip Select Module
TAEN
WS1
9
1
1
1
CSEN
WS0
Bit 8
Bit 0
1
0
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