MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 22

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table of Contents
Advance Information
22
19.5
19.5.1
19.5.2
19.6
19.6.1
19.6.1.1
19.6.1.2
19.6.2
19.6.2.1
19.6.2.2
19.6.3
19.6.4
19.6.5
19.6.6
19.6.7
19.6.8
19.7
19.8
19.8.1
19.8.2
19.8.3
19.8.4
19.8.5
19.8.5.1
19.8.5.2
19.8.5.3
19.8.6
19.8.6.1
19.8.6.2
19.8.7
19.8.8
19.8.8.1
19.8.8.2
19.8.8.3
Freescale Semiconductor, Inc.
For More Information On This Product,
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
Port QA Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Port QB Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
External Trigger Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . 434
Multiplexed Address Output Pins . . . . . . . . . . . . . . . . . . . . 434
Multiplexed Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . 435
Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Dedicated Analog Supply Pins . . . . . . . . . . . . . . . . . . . . . . 435
Dedicated Digital I/O Port Supply Pin. . . . . . . . . . . . . . . . . 435
QADC Module Configuration Register (QADCMCR) . . . . .437
QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . .438
Port Data Registers (PORTQA and PORTQB) . . . . . . . . .438
Port QA and QB Data Direction Register
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453
Conversion Command Word Table (CCW) . . . . . . . . . . . . 463
Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468
Port QA Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . .432
Port QA Digital Input/Output Pins . . . . . . . . . . . . . . . . . 433
Port QB Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . .433
Port QB Digital Input Pins . . . . . . . . . . . . . . . . . . . . . . .433
QADC Control Register 0 (QACR0) . . . . . . . . . . . . . . . . 442
QADC Control Register 1 (QACR1) . . . . . . . . . . . . . . . . 445
QADC Control Register 2 (QACR2) . . . . . . . . . . . . . . . . 448
QADC Status Register 0 (QASR0). . . . . . . . . . . . . . . . . 453
QADC Status Register 1 (QASR1). . . . . . . . . . . . . . . . . 462
Right-Justified Unsigned Result Register (RJURR) . . . . 468
Left-Justified Signed Result Register (LJSRR) . . . . . . . 469
Left-Justified Unsigned Result Register (LJURR) . . . . . 470
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(DDRQA and DDRQB) . . . . . . . . . . . . . . . . . . . . . . . . . 440
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