MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 419

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
Clock skew between the master and slave can cause data to be lost
when:
The synchronized SS signal is synchronized to the SPI clock.
18-13
SPI clock cycle late. While the synchronized SS of the slave is high,
writing is allowed even though the SS pin is already low. The write can
change the MISO pin while the master is sampling the MISO line. The
first bit of the transfer may not be stable when the master samples it, so
the byte sent to the master may be corrupted.
Figure 18-13. Transmission Error Due to Master/Slave Clock Skew
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Freescale Semiconductor, Inc.
For More Information On This Product,
CPHA = 0, and,
The baud rate is the SPI clock divided by two, and
The master SCK frequency is half the slave SPI clock frequency,
and
Software writes to the slave SPIDR just before the synchronized
SS signal goes low.
shows an example with the synchronized SS signal almost a full
Serial Peripheral Interface Module (SPI)
Go to: www.freescale.com
SS SYNCHRONIZED
SCK (CPOL = 0)
SCK (CPOL = 1)
TO SPI CLOCK
MOSI/MISO
CHANGE O
CHANGE O
SPI CLOCK
SAMPLE I
MOSI PIN
MISO PIN
SS PIN (I)
MISO PIN
SPIDR WRITE
THIS CYCLE
Serial Peripheral Interface Module (SPI)
Functional Description
Advance Information
Figure
419