MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 161

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4.8 FLASH
6.4.9 Queued Analog-to-Digital Converter (QADC)
6.4.10 Watchdog Timer
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The FLASH is in a low-power state if not being accessed. No recovery
time is required after exit from any low-power mode.
Setting the queued analog-to-digital converter (QADC) STOP bit
(QSTOP) will disable the QADC.
The QADC is unaffected by either wait or doze mode and may generate
an interrupt to exit these modes.
Low-power stop mode (or setting the QSTOP bit), immediately freezes
operation, register values, state machines, and external pins. This stops
the clock signals to the digital electronics of the module and eliminates
the quiescent current draw of the analog electronics. Any conversion
sequences in progress are stopped. Exit from low-power stop mode (or
clearing the QSTOP bit), returns the QADC to operation from the state
prior to stop mode entry, but any conversions in progress are undefined
and the QADC requires recovery time (t
Characteristics) to stabilize the analog circuits before new conversions
can be performed.
In stop mode (or in wait/doze mode, if so programmed), the watchdog
ceases operation and freezes at the current value.When exiting these
modes, the watchdog resumes operation from the stopped value. It is
the responsibility of software to avoid erroneous operation.
When not stopped, the watchdog may generate a reset to exit the
low-power modes.
Freescale Semiconductor, Inc.
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Power Management
Peripheral Behavior in Low-Power Modes
SR
in
23.9 QADC Electrical
Advance Information
Power Management
161