MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 197

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Source
10
12
13
14
15
16
17
18
19
20
21
22
11
0
1
2
3
4
5
6
7
8
9
Module
TIM1
ADC
SCI1
SCI2
SPI
PAOVF Pulse accumulator overflow
MODF Mode fault
RDRF Receive Data Register full
RDRF Receive Data Register full
TDRE
TDRE
SPIF
IDLE
IDLE
PAIF
CF1
CF2
C0F
C1F
C2F
C3F
TOF
Flag
PF1
PF2
OR
OR
TC
TC
Queue 1 conversion pause
Queue 1 conversion complete Write CF1 = 0 after reading CF1 = 1
Queue 2 conversion pause
Queue 2 conversion complete Write CF2 = 0 after reading CF2 = 1
Transfer complete
Transmit Data Register empty Write SCIDRL after reading TDRE = 1
Transmit complete
Receiver overrun
Receiver line idle
Transmit Data Register empty Write SCIDRL after reading TDRE = 1
Transmit complete
Receiver overrun
Receiver line idle
Timer channel 0
Timer channel 1
Timer channel 2
Timer channel 3
Timer overflow
Pulse accumulator input
Table 8-6. Interrupt Source Assignment
Freescale Semiconductor, Inc.
For More Information On This Product,
Source Description
Go to: www.freescale.com
Interrupt Controller Module
Access SPIDR after reading SPIF = 1
Write SCIDRL after reading TC = 1
Read SCIDRL after reading RDRF = 1
Read SCIDRL after reading OR = 1
Read SCIDRL after reading IDLE = 1
Read SCIDRL after reading RDRF = 1
Read SCIDRL after reading OR = 1
Read SCIDRL after reading IDLE = 1
Write PF1 = 0 after reading PF1 = 1
Write PF2 = 0 after reading PF2 = 1
Write to SPICR1 after reading MODF = 1
Write SCIDRL after reading TC = 1
Write C0F = 1 or access IC/OC if TFFCA = 1
Write 1 to C1F or access IC/OC if TFFCA = 1
Write 1 to C2F or access IC/OC if TFFCA = 1
Write 1 to C3F or access IC/OC if TFFCA = 1
Write TOF = 1 or access TIMCNTH/L if TFFCA = 1
Write PAIF = 1 or access PAC if TFFCA = 1
Write PAOVF = 1 or access PAC if TFFCA = 1
Flag Clearing Mechanism
Interrupt Controller Module
Continued on next page
Functional Description
Advance Information
197