MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 448

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
19.8.5.3 QADC Control Register 2 (QACR2)
Advance Information
448
Address: 0x00ca_000e and 0x00ca_000f
Reset:
Reset:
Read:
Read:
Write:
Write:
QADC Control Register 2 (QACR2) is the mode control register for
queue 2. This register governs queue operating mode and the use of
completion and/or pause interrupts. Typically, these bits are written once
when the QADC is initialized and not changed thereafter.
Stop mode resets this register ($007f).
Read: Anytime
Write: Anytime except during stop mode
CIE2 — Queue 2 Completion Software Interrupt Enable Bit
CIE2 enables an interrupt request upon completion of queue 2. The
interrupt request is initiated when the conversion is complete for the
last CCW in queue 2.
Freescale Semiconductor, Inc.
RESUME
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enable queue 2 completion interrupts.
0 = Disable queue 2 completion interrupts.
Bit 15
CIE2
Bit 7
0
0
Figure 19-10. QADC Control Register 2 (QACR2)
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BQ26
PIE2
14
0
6
1
SSE2
BQ25
13
0
0
5
1
MQ212
BQ24
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
12
0
4
1
MQ211
BQ23
11
0
3
1
MQ210
BQ22
10
0
2
1
MQ29
BQ21
9
0
1
1
MOTOROLA
MQ28
BQ20
Bit 8
Bit 0
0
1