MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 172

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

M•CORE M210 Central Processor Unit (CPU)
7.7 Operand Addressing Capabilities
7.8 Instruction Set Overview
Advance Information
172
The M•CORE processor accesses all memory operands through load
and store instructions, transferring data between the general-purpose
registers and memory. Register-plus-four-bit scaled displacement
addressing mode is used for load and store instructions addressing byte,
half-word, and word data.
Load and store multiple instructions allow a subset of the 16
general-purpose registers to be transferred to or from a base address
pointed to by register R0 (the default stack pointer by convention).
Load and store register quadrant instructions use register indirect
addressing to transfer a register quadrant to or from memory.
The instruction set is tailored to support high-level languages and is
optimized for those instructions most commonly executed. A standard
set of arithmetic and logical instructions is provided, as well as
instruction support for bit operations, byte extraction, data movement,
control flow modification, and a small set of conditionally executed
instructions which can be useful in eliminating short conditional
branches.
Table 7-1
to the M•CORE Reference Manual (Motorola document order number
MCORERM/AD) for more details on instruction operation.
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
is an alphabetized listing of the M•CORE instruction set. Refer
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA