MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 158

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power Management
6.4 Peripheral Behavior in Low-Power Modes
6.4.1 Reset
6.4.2 Clocks
Advance Information
158
A power-on reset (POR) will always cause a chip reset and exit from any
low-power mode.
In wait and doze modes, asserting the external RESET pin for at least
four clocks will cause an external reset that will reset the chip and exit
any low-power modes.
In stop mode, the RESET pin synchronization is disabled and asserting
the external RESET pin will asynchronously generate an internal reset
and exit any low-power modes. Registers will loose current values and
must be reconfigured from reset state if needed.
If the phase lock loop (PLL) is active, then any loss of clock or loss of
lock will reset the chip and exit any low-power modes.
If the watchdog timer is still enabled during wait or doze modes, then a
watchdog timer timeout may generate a reset to exit these low-power
modes.
When the CPU is inactive, a software reset can not be generated to exit
any low-power mode.
During the low power wait and doze modes, the clocks to the CPU,
FLASH, and random-access memory (RAM) will be stopped and the
system clocks to the peripherals are enabled. Each module may disable
the module clocks locally at the module level. During the low-power stop
mode, all clocks to the system will be stopped.
During stop mode, there are several options for enabling/disabling the
PLL and/or crystal oscillator (OSC) compromising between wakeup
recovery time and stop mode power. The PLL may be disabled during
stop. A wakeup time of up to 200 s is required for the PLL to re-lock.
The OSC may also be disabled during STOP. A wakeup time required
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Power Management
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA