MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 568

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
22.5.2 IDCODE Instruction
Advance Information
568
The IDCODE instruction selects the 32-bit IDCODE Register for
connection as a shift path between the TDI pin and the TDO pin. This
instruction allows interrogation of the device to determine its version
number and other part identification data. The IDCODE Register has
been implemented in accordance with the IEEE 1149.1 standard so that
the least significant bit of the shift register stage is set to logic 1 on the
rising edge of TCLK following entry into the capture-DR state. Therefore,
the first bit to be shifted out after selecting the IDCODE Register is
EXTEST
IDCODE
SAMPLE/PRELOAD
ENABLE_MCU_ONCE
HIGHZ
CLAMP
BYPASS
Reserved
Reserved
1. To exit this instruction, the TRST pin must be asserted or power-on reset.
2. Motorola reserves the right to change the decoding of the unused opcodes in the future.
Freescale Semiconductor, Inc.
For More Information On This Product,
Instruction
JTAG Test Access Port and OnCE
Go to: www.freescale.com
Table 22-1. JTAG Instructions
1010–1011
1101–1110
IR3–IR0
0101
0000
0001
0010
1001
0100
1000
0011
1100
0110
0111
1111
(1)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Selects the Boundary Scan Register while
Selects the IDCODE Register for shift
Selects the Boundary Scan Register for
Instruction to enable the M•CORE TAP
Selects the Bypass Register while
Selects bypass while applying fixed values to
Selects the Bypass Register for data
Instruction for chip manufacturing purposes
Decoded to select the Bypass Register
applying fixed values to output pins and
asserting functional reset
shifting, sampling, and preloading without
disturbing functional operation
controller
three-stating all output pins and asserting
functional reset
output pins and asserting functional reset
operations
only
Instruction Summary
MOTOROLA
(2)