MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 535

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.7.1 Read Cycles
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
1. SET R/W TO READ.
2. DRIVE ADDRESS ON A[22:0].
3. DRIVE TSIZ[1:0] PINS FOR OPERAND SIZE.
4. ASSERT CS IF USED.
5. ASSERT OE AND EB IF USED.
1. RECEIVE DATA FROM D[31:16] AND/OR D[15:0].
2. DRIVE DATA TO INTERNAL DATA BUS.
3. NEGATE OE AND EB.
1. NEGATE EB AND CS IF USED.
MMC2114, MMC2113, AND MMC2112
START NEXT CYCLE
TERMINATE CYCLE
ADDRESS DEVICE
ACQUIRE DATA
During a read cycle, the EBI receives data from an external memory or
peripheral device. During external read cycles, the OE pin is asserted
regardless of operand size. See
Figure 20-4
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 20-1. Read Cycle Flowchart
External Bus Interface Module (EBI)
Go to: www.freescale.com
for read cycle timing diagrams with and without wait states.
1. RECEIVE CS.
2. DECODE ADDRESS.
3. PUT DATA ON D[31:16] AND/OR D[15:0].
4. ASSERT TA IF NECESSARY FROM SLAVE DEVICE.
1. REMOVE DATA FROM D[31:16] AND/OR D[15:0].
2. NEGATE TA.
Figure
EXTERNAL PERIPHERAL
20-1. Also see
External Bus Interface Module (EBI)
TERMINATE CYCLE
PRESENT DATA
Advance Information
Figure 20-3
Bus Master Cycles
and
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