MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 363

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Serial Communications Interface Modules (SCI1 and SCI2)
WAKE — Wakeup Bit
ILT — Idle Line Type Bit
PE — Parity Enable Bit
PT — Parity Type Bit
This read/write bit selects the condition that wakes up the SCI
receiver when it has been placed in a standby state by setting the
RWU bit in SCICR2. When WAKE is set, a logic 1 (address mark) in
the most significant bit position of a received data character wakes the
receiver. An idle condition on the RXD pin does so when WAKE = 0.
Reset clears WAKE.
This read/write bit determines when the receiver starts counting logic
1s as idle character bits. The counting begins either after the start bit
or after the stop bit. If the count begins after the start bit, then a string
of logic 1s preceding the stop bit may cause false recognition of an
idle character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears ILT.
This read/write bit enables the parity function. When enabled, the
parity function inserts a parity bit in the most significant bit position of
an SCI data word. Reset clears PE.
This read/write bit selects even parity or odd parity. With even parity,
an even number of 1s clears the parity bit and an odd number of 1s
sets the parity bit. With odd parity, an odd number of 1s clears the
parity bit and an even number of 1s sets the parity bit. Reset clears
PT.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Address mark receiver wakeup
0 = Idle line receiver wakeup
1 = Idle frame bit count begins after stop bit.
0 = Idle frame bit count begins after start bit.
1 = Parity function enabled
0 = Parity function disabled
1 = Odd parity when PE = 1
0 = Even parity when PE = 1
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Serial Communications Interface Modules (SCI1 and SCI2)
Memory Map and Registers
Advance Information
363