MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 543

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.9.4 Transfer Code (TC[2:0])
20.9.5 Processor Status (PSTAT)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Figure 20-6. Internal (Show) Cycle Followed by External 1-Clock Write
A{22:0], TSIZ[1:0]
CLKOUT
CSE[1:0]
TA, TEA
EB[3:0]
D[31:0]
SHS
R/W
CS
OE
These signals are outputs from a master and inputs to a slave device.
They are enabled by default in emulation mode and can be enabled in
other modes by setting PEPA[2:0] of Port E Pin Assignment Register
(PEPAR). See
signals identify the processor state (supervisor or user) and the address
space of the current bus cycle. The space and state are defined in
Table
These signals are outputs from the CPU and may be applied to external
pins (INT[5:2]). They are enabled by default in emulation mode and can
be enabled in other modes by setting PSTEN of CCR. See
Configuration
events occurring within the core, and may be monitored by a debug
block to condition events, and/or may be reflected off-chip as well.
Table 20-6
Freescale Semiconductor, Inc.
For More Information On This Product,
20-5.
External Bus Interface Module (EBI)
INTERNAL CYCLE
shows the definitions of the processor status encoding.
Go to: www.freescale.com
12.4.2.6 Port E Pin Assignment
Register. The PSTAT pins indicate the internal state and
A1
SHOW
D1
EXTERNAL WRITE
DATA
A2
00
External Bus Interface Module (EBI)
D2
Register. These
Advance Information
Emulation Support
4.7.3.1 Chip
543