MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 478

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
19.10 Digital Control
19.10.1 Queue Priority Timing Examples
19.10.1.1 Queue Priority
Advance Information
478
The digital control subsystem includes the control logic to sequence the
conversion activity, the clock and periodic/interval timer, control and
status registers, the conversion command word table RAM, and the
result word table RAM.
The central element for control of QADC conversions is the 64-entry
conversion command word (CCW) table. Each CCW specifies the
conversion of one input channel. Depending on the application, one or
two queues can be established in the CCW table. A queue is a scan
sequence of one or more input channels. By using a pause mechanism,
subqueues can be created in the two queues. Each queue can be
operated using one of several different scan modes. The scan modes for
queue 1 and queue 2 are programmed in control registers QACR1 and
QACR2. Once a queue has been started by a trigger event (any of the
ways to cause the QADC to begin executing the CCWs in a queue or
subqueue), the QADC performs a sequence of conversions and places
the results in the result word table.
This subsection describes the QADC priority scheme when trigger
events on two queues overlap or conflict.
Queue 1 has priority over queue 2 execution. These cases show the
conditions under which queue 1 asserts its priority:
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
When a queue is not active, a trigger event for queue 1 or queue
2 causes the corresponding queue execution to begin.
When queue 1 is active and a trigger event occurs for queue 2,
queue 2 cannot begin execution until queue 1 reaches completion
or the paused state. The status register records the trigger event
by reporting the queue 2 status as trigger pending. Additional
trigger events for queue 2, which occur before execution can
begin, are flagged as trigger overruns.
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA