MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 586

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
22.14.3.2 CPU Debug Request (DBGRQ)
22.14.3.3 CPU Debug Acknowledge (DBGACK)
22.14.3.4 CPU Breakpoint Request (BRKRQ)
Advance Information
586
DBGACK
DBGRQ
BRKRQ
DEBUG
PSTAT
ADDR
ATTR
IDR
INFORMATION
PIPELINE
The DBGRQ signal is asserted by the OnCE control logic to request the
CPU to enter the debug state. It may be asserted for a number of
different conditions. Assertion of this signal causes the CPU to finish the
current instruction being executed, save the instruction pipeline
information, enter debug mode, and wait for further commands.
Asserting DBGRQ causes the device to exit stop, doze, or wait mode.
The CPU asserts the DBGACK signal upon entering the debug state.
This signal is part of the handshake mechanism between the OnCE
control logic and the CPU.
The BRKRQ signal is asserted by the OnCE control logic to signal that
a breakpoint condition has occurred for the current CPU bus access.
FIFO
PC
Freescale Semiconductor, Inc.
Figure 22-8. OnCE Interface Diagram
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
COMPARATORS
BREAKPOINT
REGISTERS
TRACE LOGIC
AND
BREAKPOINT
AND
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
CONTROLLER
INTERFACE
SERIAL
OnCE
AND
TDI
TCK
TMS
TDO
TRST
DE
MOTOROLA