MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 170

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

M•CORE M210 Central Processor Unit (CPU)
Advance Information
170
The supervisor programming model consists of the user model plus 16
additional 32-bit general-purpose registers (R0–R15), called the
alternate file and a set of status/control registers (CR0–CR12) which
includes the entire PSR. Setting the S bit in the PSR enables supervisor
mode operation.
The alternate file allows very low overhead context switching for
real-time event handling. While the alternate file is enabled,
general-purpose registers are accessed from it.
The Vector Base Register (VBR) determines the base address of the
exception vector table. Exception shadow registers EPC and EPSR are
used to save the states of the program counter and PSR, respectively,
when an exception occurs. Shadow registers FPC and FPSR save the
states of the program counter and PSR, respectively, when a fast
interrupt exception occurs.
Five scratch registers (SS0–SS4) are used to handle exception events.
The global control (GCR) and status (GSR) registers can be used for a
variety of system monitoring tasks at the discretion of the compiler used.
They serve no specific function by or for the CPU.
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
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