MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 652

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Security
Advance Information
652
NOTE:
blocked in such a way that the JTAG boundary scan feature is still usable
when security is enabled. Please refer to
Access Port and OnCE
operation.
If security is inadvertently enabled on the MCU, a lockout recovery
mechanism allows the on-chip FLASH to be completely erased
(including the configuration field), thus disabling security. This does not
compromise security as all FLASH physical blocks are erased before
security is disabled during the next reset or power-up sequence. To
activate lockout recovery, the JTAG public instruction
LOCKOUT_RECOVERY must first be shifted into the top level TAP
controller’s instruction register. The LOCKOUT_RECOVERY instruction
has an associated 7-bit data register that is used to control the clock
divider circuit within the SGFM module. This divider controls the
frequency of the SGFM state machine clock and must be set with an
appropriate value before the lockout recovery sequence can begin.
Refer to
for more details on setting this register value.
Once the LOCKOUT_RECOVERY instruction has been shifted into the
instruction register, the clock divider value must be shifted into the
corresponding 7-bit data register. After the data register has been
updated, the user must transition the TAP controller into the
RUN-TEST/IDLE state for the lockout recovery sequence to commence.
The controller must remain in the RUN-TEST/IDLE state until the erase
sequence is complete. See
OnCE
It is important to note that the LOCKOUT_RECOVERY instruction is only
effective on a secured MCU. Using this instruction on an unsecured
device has no effect.
Once the lockout recovery sequence is complete, both the JTAG TAP
controller (by asserting TRST) and the MCU (by asserting RESET) must
be reset to resume normal unsecured operation.
Freescale Semiconductor, Inc.
For More Information On This Product,
for further details on controlling transitions of the TAP controller.
Section 10. Second Generation FLASH for M•CORE (SGFM)
Go to: www.freescale.com
Security
for further information on boundary scan
Section 22. JTAG Test Access Port and
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Section 22. JTAG Test
MOTOROLA