MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 128

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chip Configuration Module (CCM)
Advance Information
128
NOTE:
SZEN — TSIZ[1:0] Enable Bits
PSTEN — PSTAT[3:0] Signal Enable Bits
SHINT — Show Interrupt Bit
The FRCRSTOUT function in the reset controller has a higher priority
than the SHINT function.
BME — Bus Monitor External Enable Bit
BMD — Bus Monitor Debug Mode Bit
This read/write bit enables the TSIZ[1:0] function of the external pins.
This read/write bit enables the PSTAT[3:0] function of the external
pins.
The SHINT bit allows visibility to any active interrupt request to the
processor. If the SHINT bit is set, the RSTOUT pin is the OR of the
fast and normal interrupt signals.
The SHINT bit is read/write always.
The BME bit enables the bus monitor to operate during external bus
cycles.
Table 4-2
The BMD bit controls how the bus monitor responds during debug
mode.
This bit is read/write always.
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1 = TSIZ[1:0] function enabled
0 = TSIZ[1:0] function disabled
1 = PSTAT[3:0] function enabled
0 = PSTAT[3:0] function disabled
1 = Internal requests reflected on RSTOUT pin
0 = Normal RSTOUT pin function
1 = Bus monitor enabled for external bus cycles
0 = Bus monitor disabled for external bus cycles
1 = Bus monitor enabled in debug mode
0 = Bus monitor disabled in debug mode
Chip Configuration Module (CCM)
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shows the read/write accessibility of this write-once bit.
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
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