MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 545

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.10 Bus Monitor
20.11 Interrupts
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The bus monitor can be set to detect excessively long bus access
termination response times. Whenever an undecoded address is
accessed or a peripheral is inoperative, the access is not terminated and
the bus is potentially locked up while it waits for the required response.
The bus monitor monitors the cycle termination response time during a
bus cycle. If the cycle termination response time exceeds a programmed
count, the bus monitor asserts an internal bus error.
The bus monitor monitors the cycle termination response time (in system
clock cycles) by using a programmable maximum allowable response
period. There are four selectable response time periods for the bus
monitor, selectable among 8, 16, 32, and 64 system clock cycles. The
periods are selectable with the BMT[1:0] field in the chip configuration
module CCR (see
programmability of the timeout allows for varying external peripheral
response times. The monitor is cleared and restarted on all bus
accesses. If the cycle is not terminated within the selected response
time, a timeout occurs and the bus monitor terminates the bus cycle.
The bus monitor can be configured with the BME bit in the chip
configuration module CCR to monitor only internal bus accesses or both
internal and external bus accesses. Also, the bus monitor can be
disabled during debug mode for both internal and external accesses.
Two external bus cycles are required for a single 32-bit access to a 16-bit
port. If the bus monitor is enabled to monitor external accesses, then the
bus monitor views the 32-bit access as two separate external bus cycles
and not as one internal bus cycle.
The EBI does not generate interrupt requests.
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
Go to: www.freescale.com
4.7.3.1 Chip Configuration
External Bus Interface Module (EBI)
Register). The
Advance Information
Bus Monitor
545