MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 65

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MMC2114CFCAG33

Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheets

Specifications of MMC2114CFCAG33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Chip Selects (CS)
P = Current pin state
0x00c2_0000
0x00c2_0001
0x00c2_0002
0x00c2_0003
0x00c2_0004
0x00c2_0005
Address
Register Name
Register 0 (CSCR0)
Register 1 (CSCR1)
Register 2 (CSCR2)
Chip Select Control
Chip Select Control
Chip Select Control
U = Unaffected
See page 551.
See page 552.
See page 552.
Figure 2-4. Register Summary (Sheet 9 of 37)
Freescale Semiconductor, Inc.
For More Information On This Product,
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Note: Reset state determined during reset configuration.
Note: Reset state determined during reset configuration
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
SO
SO
SO
Go to: www.freescale.com
0
0
0
0
0
0
0
0
0
System Memory Map
= Writes have no effect and the access terminates without a transfer error exception.
RO
RO
RO
14
14
14
0
6
0
0
0
6
0
0
0
6
0
0
See note
PS
PS
PS
13
13
13
5
0
0
1
5
0
0
1
5
0
0
WWS
WWS
WWS
12
12
12
1
4
0
0
1
4
0
0
1
4
0
0
Bit Number
WE
WE
WE
11
11
11
1
3
0
0
1
3
0
0
1
3
0
0
WS2
WS2
WS2
10
10
10
1
2
0
0
1
2
0
0
1
2
0
0
System Memory Map
Advance Information
TAEN
TAEN
TAEN
WS1
WS1
WS1
9
1
1
1
9
1
1
1
9
1
1
1
Register Map
See note
See note
CSEN
CSEN
CSEN
WS0
WS0
WS0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
1
1
1
0
65

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