MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 457

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
TOR1 — Queue 1 Trigger Overrun Flag
TOR2 — Queue 2 Trigger Overrun Flag
TOR1 indicates that an unexpected trigger event has occurred for
queue 1. TOR1 can be set only while queue 1 is in the active state.
A trigger event generated by a transition on the external trigger pin or
by the periodic/interval timer may be captured as a trigger overrun.
TOR1 cannot be set when the software-initiated single-scan mode or
the software-initiated continuous-scan mode is selected.
TOR1 is set when a trigger event is received while a queue is
executing and before the scan has completed or paused. TOR1 has
no effect on queue execution.
After a trigger event has occurred for queue 1, and before the scan
has completed or paused, additional queue 1 trigger events are not
retained. Such trigger events are considered unexpected, and the
QADC sets the TOR1 error status bit. An unexpected trigger event
may denote a system overrun situation.
In externally gated continuous-scan mode, the behavior of TOR1 has
been redefined. In the case when queue 1 reaches an end-of-queue
condition for the second time during an open gate, TOR1 is set. This
is considered an overrun condition. In this case CF1 has been set for
the first end-of-queue 1 condition and then TOR1 sets for the second
end-of-queue 1 condition. For TOR1 to set, CF2 must not be cleared
before the second end-of-queue 1.
Once set, TOR1 is cleared only by a reset or by writing a 0 to it.
TOR2 indicates that an unexpected trigger event has occurred for
queue 2. TOR2 can be set when queue 2 is in the active, suspended,
and trigger pending states.
The TOR2 trigger overrun can occur only when using an external
trigger mode or a periodic/interval timer mode. Trigger overruns
cannot occur when the software-initiated single-scan mode and the
software-initiated continuous-scan mode are selected.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = At least one unexpected queue 1 trigger event has occurred or
0 = No unexpected queue 1 trigger events have occurred.
queue 1 reaches an end-of-queue condition for the second
time in externally gated continuous scan.
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
Advance Information
457