MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 27

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MMC2114CFCAG33

Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheets

Specifications of MMC2114CFCAG33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
22.14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
22.14.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
22.14.2 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . . 584
22.14.3 OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
22.14.3.1
22.14.3.2
22.14.3.3
22.14.3.4
22.14.3.5
22.14.3.6
22.14.3.7
22.14.4 OnCE Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . 587
22.14.4.1
22.14.4.2
22.14.4.3
22.14.5 OnCE Decoder (ODEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
22.14.6 Memory Breakpoint Logic. . . . . . . . . . . . . . . . . . . . . . . . . . 596
22.14.6.1
22.14.6.2
22.14.7 Breakpoint Address Mask Registers . . . . . . . . . . . . . . . . . 597
22.14.7.1
22.14.7.2
22.14.8 OnCE Trace Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
22.14.8.1
22.14.8.2
22.14.9 Methods of Entering Debug Mode . . . . . . . . . . . . . . . . . . . 600
22.14.9.1
22.14.9.2
22.14.9.3
22.14.9.4
22.14.10 Enabling OnCE Trace Mode . . . . . . . . . . . . . . . . . . . . . . .601
22.14.11 Enabling OnCE Memory Breakpoints. . . . . . . . . . . . . . . . . 602
22.14.12 Pipeline Information and Write-Back Bus Register . . . . . . 602
22.14.12.1 Program Counter Register . . . . . . . . . . . . . . . . . . . . . . .603
22.14.12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
22.14.12.3 Control State Register . . . . . . . . . . . . . . . . . . . . . . . . . . 603
22.14.12.4 Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . 605
Freescale Semiconductor, Inc.
For More Information On This Product,
Internal Debug Request Input (IDR) . . . . . . . . . . . . . . . 585
CPU Debug Acknowledge (DBGACK) . . . . . . . . . . . . . .586
CPU Breakpoint Request (BRKRQ). . . . . . . . . . . . . . . . 586
CPU Address, Attributes (ADDR, ATTR) . . . . . . . . . . . . 587
CPU Status (PSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . .588
OnCE Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 590
OnCE Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Memory Address Latch (MAL) . . . . . . . . . . . . . . . . . . . . 597
Breakpoint Address Base Registers . . . . . . . . . . . . . . . 597
Breakpoint Address Comparators . . . . . . . . . . . . . . . . . 598
Memory Breakpoint Counters . . . . . . . . . . . . . . . . . . . . 598
OnCE Trace Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Trace Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Debug Request During RESET . . . . . . . . . . . . . . . . . . .600
Debug Request During Normal Activity . . . . . . . . . . . . . 601
Debug Request During Stop, Doze, or Wait Mode . . . .601
Software Request During Normal Activity . . . . . . . . . . . 601
CPU Debug Request (DBGRQ) . . . . . . . . . . . . . . . . . . .586
OnCE Debug Output (DEBUG) . . . . . . . . . . . . . . . . . . . 587
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Advance Information
Table of Contents
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