MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 115

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.5.3.3 Transfer Acknowledge (TA)
3.5.3.4 Transfer Error Acknowledge (TEA)
3.5.3.5 Emulation Mode Chip Selects (CSE[1:0])
3.5.3.6 Transfer Code (TC[2:0])
3.5.3.7 Read/Write (R/W)
3.5.3.8 Address Bus (A[22:0])
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
This input signal indicates that the external data transfer is complete.
During a read cycle, when the processor recognizes TA, it latches the
data and then terminates the bus cycle. During a write cycle, when the
processor recognizes TA, the bus cycle is terminated. This signal is an
input in master and emulation modes. This function is not used in single-
chip mode and its pin defaults to digital I/O.
This signal indicates an error condition exists for the bus transfer. The
bus cycle is terminated and the central processor unit (CPU) begins
execution of the access error exception. This signal is an input in master
and emulation modes. This function is not used in single-chip mode and
its pin defaults to digital I/O.
These output signals provide chip select support in emulation mode.
These output signals indicate the data transfer code for the current bus
cycle. These signals are enabled by default only in emulation mode. See
Table 12-2. PEPAR Reset
This output signal indicates the direction of the data transfer on the bus.
A logic 1 indicates a read from a slave device and a logic 0 indicates a
write to a slave device.
These output signals provide the address for the current bus transfer.
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Signal Description
Values.
Advance Information
Signal Descriptions
Signal Description
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