MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 541

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.9.2 Internal Data Transfer Display (Show Cycles)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Accesses to the address space which contains the registers for the
internal modules (except ports) are indicated by CSE[1:0] = 11.
Internal accesses, other than to the specific module control registers, are
indicated by CSE[1:0] = 01. It should be noted that at higher frequencies
writes to external memories emulating the internal memories may
require one clock for read accesses and two clocks for write accesses.
Internal data transfers normally occur without showing the internal data
bus activity on the external data bus. For debugging purposes, however,
it may be desirable to have internal cycle data appear on the external
bus. These external bus cycles are referred to as show cycles and are
distinguished from normal external cycles by the fact that OE and
EB[3:0] remain negated.
Regardless of whether show cycles are enabled, the EBI drives the
address bus, TC[2:0], TSIZ[1:0] and R/W signals, indicating the internal
cycle activity. When show cycles are disabled, D[31:0] remains in a high
impedance state. When show cycles are enabled, OE and EB[3:0]
remain negated while the internal data is presented on D[31:0] on the
first clock tick after the termination of the internal cycle.
Show cycles are always enabled in emulation mode. In master mode,
show cycles are disabled coming out of reset and must be enabled by
writing to the SHEN bit in the Chip Configuration Register (CCR).
1. CSE[1:0] is valid only for the duration of valid bus cycles or reset. Undefined otherwise.
CSE1
Freescale Semiconductor, Inc.
1
1
0
0
For More Information On This Product,
Table 20-4. Emulation Mode Chip-Select Summary
External Bus Interface Module (EBI)
CSE0
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1
0
1
0
Internal access to any register space (excluding ports)
Internal access to ports register space
Internal access not covered by CSE encoding = 11, 10
External access
Reset state
(0x00c1_0000:0x00ff_ffff)
(0x00c0_0000:0x00c0_ffff)
(0x0000_0000:0x00bf_ffff; 0x0100_0000:0x07ff_ffff)
(0x8000_0000 to 0xffff_ffff)
Indication in Emulation Mode
External Bus Interface Module (EBI)
Advance Information
Emulation Support
(1)
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