MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 488

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
Advance Information
488
QS:
Q1:
Q2:
Q1:
Q2:
QS:
0000
0000
IDLE
IDLE
Q2:
Q2:
IDLE
IDLE
T2
T2
C1
C1
ACTIVE
ACTIVE
0010
0010
Situations S10 and S11
when an additional trigger event is detected for queue 2 while the queue
is suspended, the trigger overrun error bit is set, the same as if queue 2
were being executed when a new trigger event occurs. Trigger overrun
on queue 2 thus allows the user to know that queue 1 is taking up so
much QADC time that queue 2 trigger events are being lost.
C2
C2
Q1:
Q1:
Figure 19-32. CCW Priority Situation 10
Figure 19-33. CCW Priority Situation 11
Freescale Semiconductor, Inc.
T1
T1
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
TOR2
TOR2
C1
C1
SUSPEND
SUSPEND
ACTIVE
ACTIVE
T2
T2
1010
1010
C2
C2
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PF1
PF1
0110
ACT
C1
C2
ACTIVE
0110
PF2
PAUSE
0101
C2
PAUSE
PAUSE
PF2
T2
PAUSE
0101
(Figure 19-32
C3
ACTIVE
0110
T2
0110
ACT
C3
C4
T1
T1
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
TOR2
TOR2
C3
SUSPEND
C3
SUSPEND
ACTIVE
ACTIVE
T2
T2
1010
1010
C4
C4
and
CF1
CF1
ACT
0010
C3
Figure
C4
ACTIVE
0010
CF2
C4
RESUME = 1
CF2
19-33) show that
IDLE
IDLE
RESUME = 0
IDLE
0000
IDLE
0000
MOTOROLA