MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 566

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
22.4 Top-Level TAP Controller
Advance Information
566
The top-level TAP controller is responsible for interpreting the sequence
of logical values on the TMS signal. It is a synchronous state machine
that controls the operation of the JTAG logic. The machine’s states are
shown in
the value of the TMS signal sampled on the rising edge of the TCLK
signal.
The top-level TAP controller can be asynchronously reset to the test-
logic-reset state by asserting TRST, test reset. As
holding TMS high (to logic 1) while clocking TCLK through at least five
rising edges will also cause the state machine to enter its test-logic-reset
state.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 22-2. Top-Level TAP Controller State Machine
Figure
1
0
JTAG Test Access Port and OnCE
RUN-TEST/IDLE
Go to: www.freescale.com
TEST-LOGIC-
RESET
22-2. The value shown adjacent to each arc represents
0
1
1
0
1
SELECT-DR_SCAN
CAPTURE-DR
UPDATE-DR
PAUSE-DR
SHIFT-DR
EXIT1-DR
EXIT2-DR
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
0
0
1
0
1
1
0
0
0
1
1
1
0
1
SELECT-IR_SCAN
CAPTURE-IR
Figure 22-2
UPDATE-IR
PAUSE-IR
SHIFT-IR
EXIT1-IR
EXIT2-IR
0
0
1
0
1
1
0
0
0
1
MOTOROLA
1
shows,
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