MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 222

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Second Generation FLASH for M•CORE (SGFM)
10.7.2.2 SGFM Supervisor Access Register
Advance Information
222
Address: 0x00d0_0014 and 0x00d0_0015
The SGFM Supervisor Access Register (SGFMSACC) is banked and
specifies the supervisor/user access permissions of FLASH logical
sectors.
SUPV[15:0] — Supervisor Address Space Assignment Bits
Figure 10-10. SGFM Supervisor Access Register (SGFMASACC)
Reset:
Reset:
Read:
Read:
Write:
Write:
The SUPV[15:0] bits are always readable and only writable when
LOCK = 0. Each FLASH logical sector can be mapped into supervisor
or unrestricted address space. SGFMSACC uses the same
correspondence between logical sectors and register bits as does
SGFMPROT. See
When a logical sector is mapped into supervisor address space, only
CPU supervisor accesses will be allowed. A CPU user access to a
location in supervisor address space will result in a cycle termination
transfer error. When a logical sector is mapped into unrestricted
address space both supervisor and user accesses are allowed.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
1 = Logical sector is mapped in supervisor address space.
0 = Logical sector is mapped in unrestricted address space.
Note 1. Reset state loaded from FLASH configuration field during reset.
SUPV15
SUPV7
Bit 15
Bit 7
F
F
(1)
(1)
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SUPV14
SUPV6
F
F
14
6
(1)
(1)
Figure 10-9
SUPV13
SUPV5
F
F
13
5
(1)
(1)
SUPV12
SUPV4
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
F
F
12
for details.
4
(1)
(1)
SUPV11
SUPV3
F
F
11
3
(1)
(1)
SUPV10
SUPV2
F
F
10
2
(1)
(1)
SUPV9
SUPV1
F
F
9
1
(1)
(1)
MOTOROLA
SUPV8
SUPV0
Bit 8
Bit 0
F
F
(1)
(1)