MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 584

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
22.14.2 OnCE Controller and Serial Interface
Advance Information
584
The OnCE controller is implemented as a 16-state finite state machine,
with a one-to-one correspondence to the states defined for the JTAG
TAP controller.
CPU registers and the contents of memory locations are accessed by
scanning instructions and data into and out of the CPU scan chain.
Required data is accessed by executing the scanned instructions.
Memory locations may be read by scanning in a load instruction to the
CPU that references the desired memory location, executing the load
instruction, and then scanning out the result of the load. Other resources
are accessed in a similar manner.
Resources contained in the OnCE module that do not require the CPU
to be halted for access may be controlled while the CPU is executing and
do not interfere with normal processor execution. Accesses to certain
resources, such as the PC FIFO and the count registers, while not part
of the CPU, may require the CPU to be stopped to allow access to avoid
synchronization hazards. If it is known that the CPU clock is enabled and
running no slower than the TCLK input, there is sufficient
synchronization performed to allow reads but not writes of these specific
resources. Debug firmware may ensure that it is safe to access these
resources by reading the OSR to determine the state of the CPU prior to
access. All other cases require the CPU to be in the debug state for
deterministic operation.
Figure 22-7
interface.
The OnCE Command Register (OCMR) acts as the Instruction Register
(IR) for the TAP controller. All other OnCE resources are treated as data
registers (DR) by the TAP controller. The Command Register is loaded
by serially shifting in commands during the TAP controller shift-IR state,
and is loaded during the update-IR state. The OCMR selects a OnCE
resource to be accessed as a DR during the TAP controller capture-DR,
shift-DR and update-DR states.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
is a block diagram of the OnCE controller and serial
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
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