MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 223

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.7.2.3 SGFM Data Access Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: 0x00d0_0016 and 0x00d0_0017
The SGFM Data Access Register (SGFMDACC) is banked and specifies
the data/program access permissions of FLASH logical sectors.
DATA[15:0] — Data Address Space Assignment Bits
Reset:
Reset:
Read:
Read:
Write:
Write:
The DATA[15:0] bits are always readable and only writable when
LOCK = 0. Each FLASH logical sector can be mapped into data or
both data and program address space. SGFMDACC uses the same
correspondence between logical sectors and register bits as does
SGFMPROT. See
When a logical sector is mapped into data address space, only CPU
data accesses will be allowed. A CPU program access to a location
in data address space will result in a cycle termination transfer error.
When an array sector is mapped into both data and program address
space both data and program accesses are allowed.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
Figure 10-11. SGFM Data Access Register (SGFMDACC)
For More Information On This Product,
1 = Logical sector is mapped in data address space.
0 = Logical sector is mapped in data and program address space.
Note 1. Reset state loaded from FLASH configuration field during reset.
DATA15
DATA7
Bit 15
Bit 7
F
F
(1)
(1)
Go to: www.freescale.com
DATA14
DATA6
F
F
14
6
(1)
(1)
Figure 10-9
DATA13
DATA5
F
F
13
5
(1)
(1)
Second Generation FLASH for M•CORE (SGFM)
DATA12
DATA4
F
F
12
for details.
4
(1)
(1)
DATA11
DATA3
F
F
11
3
(1)
(1)
DATA10
DATA2
F
F
10
2
(1)
(1)
Module Memory Map
Advance Information
DATA9
DATA1
F
F
9
1
(1)
(1)
DATA8
DATA0
Bit 8
Bit 0
F
F
(1)
(1)
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