MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 443

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
TRG — Trigger Assignment Bit
QPR[6:0] — Prescaler Clock Divider Bits
The TRG bit determines the queue assignment of the ETRIG[2:1]
pins.
The read/write QPR[6:0] bits select the system clock divisor to
generate the QADC clock as
clock rate can be given as:
where:
If QPR[6:0] = 0, then the QPR register field value is read as a 1 and
the prescaler divisor is 2.
The prescaler should be selected so that the QADC clock rate is
within the required fQCLK range. See
Conversion Specifications
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 <= QPR[6:0] <= 127.
1 = ETRIG1 triggers queue 2; ETRIG2 triggers queue 1.
0 = ETRIG1 triggers queue 1; ETRIG2 triggers queue 2.
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f
QCLK
=
Table 19-3
(Operating).
QPR[6:0] + 1
Queued Analog-to-Digital Converter (QADC)
f
SYS
Table 23-8. QADC
shows. The resulting QADC
Register Descriptions
Advance Information
443